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Get the FPGA part working

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This changes some of the clocks, fixes a bug in the seven segment stuff.
This commit is contained in:
Byron Lathi
2022-03-11 22:55:26 -06:00
parent cdf3da9b13
commit 3d9d340520
11 changed files with 64714 additions and 11632 deletions
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13
hw/fpga/output_files/super6502.cdf Normal file
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/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M50DAF484) Path("/home/byron/Projects/super6502/hw/fpga/output_files/") File("super6502.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;