Get the FPGA part working

This changes some of the clocks, fixes a bug in the seven segment stuff.
2022-03-11 22:55:26 -06:00
parent cdf3da9b13
commit 3d9d340520
11 changed files with 64714 additions and 11632 deletions
--- a/hw/fpga/super6502.sdc
+++ b/hw/fpga/super6502.sdc
@@ -1,7 +1,7 @@
 #**************************************************************
 # Create Clock (where ‘clk’ is the user-defined system clock name)
 #**************************************************************
-create_clock -name {clk} -period 20ns -waveform {0.000 5.000} [get_ports {clk}]
+create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk}]
 # Constrain the input I/O path
 set_input_delay -clock {clk} -max 3 [all_inputs]
 set_input_delay -clock {clk} -min 2 [all_inputs]