Add REPO_TOP env var

hw/efinix_fpga/simulation/Makefile

@@ -4,7 +4,9 @@ SRCS+=$(shell find ../src/ -type f -name "*.*v")
 
 INC=$(shell find include/ -type f)
 
-TEST_PROGRAM=../../../sw/test_code/simple_mem_test/simple_mem_test.hex
+TEST_PROGRAM_NAME=simple_mem_test
+
+TEST_PROGRAM=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
 #TODO implement something like sources.list
 
@@ -22,4 +24,4 @@ $(INIT_MEM):
 .PHONY: clean
 clean:
 	rm -rf $(TARGET)
-	rm $(INIT_MEM)
+	rm -rf $(INIT_MEM)

init_env.sh

@@ -20,6 +20,8 @@
 # export PATH=$PATH:"$EFXPT_HOME/bin"
 
 source $EFX_SETUP
+export REPO_TOP=$(git rev-parse --show-toplevel)
+
 
 # python -m venv .user_venv --system-site-packages
 # . .user_venv/bin/activate

sw/bios/Makefile

@@ -7,7 +7,7 @@ NAME=bios
 BIN=$(NAME).bin
 HEX=$(NAME).hex
 
-FPGA_IMG=../../hw/efinix_fpga/init_hex.mem
+FPGA_IMG=$(REPO_TOP)/hw/efinix_fpga/init_hex.mem
 EFX_RUN=/home/byron/Software/efinity/2023.1/scripts/efx_run.py
 EFX_PRJ=/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml