diff --git a/hw/fpga/sdram.sv b/hw/fpga/sdram.sv new file mode 100644 index 0000000..522596f --- /dev/null +++ b/hw/fpga/sdram.sv @@ -0,0 +1,87 @@ +module sdram( + input rst, + input clk_50, + input cpu_clk, + input [15:0] addr, + input sdram_cs, + input rwb, + input [7:0] data_in, + output [7:0] data_out, + + ///////// SDRAM ///////// + output wire DRAM_CLK, + output wire DRAM_CKE, + output wire [12: 0] DRAM_ADDR, + output wire [ 1: 0] DRAM_BA, + inout wire [15: 0] DRAM_DQ, + output wire DRAM_LDQM, + output wire DRAM_UDQM, + output wire DRAM_CS_N, + output wire DRAM_WE_N, + output wire DRAM_CAS_N, + output wire DRAM_RAS_N +); + +enum logic {ACCESS, WAIT } state, next_state; +logic ack; +logic _sdram_cs; + +always @(posedge clk_50) begin + if (rst) + state <= ACCESS; + else + state <= next_state; +end + +always_comb begin + next_state = state; + + case (state) + ACCESS: begin + if (sdram_cs & ~rwb & ack) + next_state = WAIT; + end + WAIT: begin + if (~cpu_clk) + next_state = ACCESS; + end + endcase +end + +always_comb begin + _sdram_cs = '0; + + case (state) + ACCESS: begin + _sdram_cs = sdram_cs & cpu_clk; + end + WAIT: begin + _sdram_cs = '0; + end + endcase +end + +sdram_platform u0 ( + .clk_clk (clk_50), // clk.clk + .reset_reset_n (1'b1), // reset.reset_n + .ext_bus_address (addr), // ext_bus.address + .ext_bus_byte_enable (1'b1), // .byte_enable + .ext_bus_read (_sdram_cs & rwb), // .read + .ext_bus_write (_sdram_cs & ~rwb), // .write + .ext_bus_write_data (data_in), // .write_data + .ext_bus_acknowledge (ack), // .acknowledge + .ext_bus_read_data (data_out), // .read_data + //SDRAM + .sdram_clk_clk(DRAM_CLK), //clk_sdram.clk + .sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr + .sdram_wire_ba(DRAM_BA), //.ba + .sdram_wire_cas_n(DRAM_CAS_N), //.cas_n + .sdram_wire_cke(DRAM_CKE), //.cke + .sdram_wire_cs_n(DRAM_CS_N), //.cs_n + .sdram_wire_dq(DRAM_DQ), //.dq + .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm + .sdram_wire_ras_n(DRAM_RAS_N), //.ras_n + .sdram_wire_we_n(DRAM_WE_N) //.we_n +); + +endmodule \ No newline at end of file diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index 55f3a8e..e6fb6fa 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -350,6 +350,7 @@ set_location_assignment PIN_V22 -to DRAM_LDQM set_location_assignment PIN_U22 -to DRAM_RAS_N set_location_assignment PIN_J21 -to DRAM_UDQM set_location_assignment PIN_V20 -to DRAM_WE_N +set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv set_global_assignment -name QIP_FILE sdram_platform/synthesis/sdram_platform.qip set_global_assignment -name SYSTEMVERILOG_FILE uart.sv set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv diff --git a/hw/fpga/super6502.sdc b/hw/fpga/super6502.sdc index b6b8652..a1b404a 100644 --- a/hw/fpga/super6502.sdc +++ b/hw/fpga/super6502.sdc @@ -3,7 +3,7 @@ #************************************************************** create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk_50}] -create_generated_clock -source [get_pins {u0|sdram_pll|sd1|pll7|clk[1] }] \ +create_generated_clock -source [get_pins {sdram|u0|sdram_pll|sd1|pll7|clk[1] }] \ -name clk_dram_ext [get_ports {DRAM_CLK}] derive_pll_clocks @@ -21,7 +21,7 @@ set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*] set_multicycle_path -from [get_clocks {clk_dram_ext}] \ - -to [get_clocks {u0|sdram_pll|sd1|pll7|clk[0] }] \ + -to [get_clocks {sdram|u0|sdram_pll|sd1|pll7|clk[0] }] \ -setup 2 set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}] diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 073a06d..8b6247d 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -26,18 +26,18 @@ module super6502( input logic UART_RXD, output logic UART_TXD, - ///////// SDRAM ///////// - output DRAM_CLK, - output DRAM_CKE, - output [12: 0] DRAM_ADDR, - output [ 1: 0] DRAM_BA, - inout [15: 0] DRAM_DQ, - output DRAM_LDQM, - output DRAM_UDQM, - output DRAM_CS_N, - output DRAM_WE_N, - output DRAM_CAS_N, - output DRAM_RAS_N + ///////// SDRAM ///////// + output DRAM_CLK, + output DRAM_CKE, + output [12: 0] DRAM_ADDR, + output [ 1: 0] DRAM_BA, + inout [15: 0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_UDQM, + output DRAM_CS_N, + output DRAM_WE_N, + output DRAM_CAS_N, + output DRAM_RAS_N ); logic rst; @@ -107,60 +107,31 @@ always_comb begin cpu_data_out = 'x; end -enum logic {S_0, S_1 } teststate, next_teststate; -logic ack; -logic write; -logic _sdram_cs; -always @(posedge clk_50) begin - if (rst) - teststate <= S_0; - else - teststate <= next_teststate; -end +sdram sdram( + .rst(rst), + .clk_50(clk_50), + .cpu_clk(cpu_phi2), + .addr(cpu_addr), + .sdram_cs(sdram_cs), + .rwb(cpu_rwb), + .data_in(cpu_data_in), + .data_out(sdram_data_out), -always_comb begin - next_teststate = teststate; - write = '0; - _sdram_cs = '0; - case (teststate) - S_0: begin - write = sdram_cs & ~cpu_rwb & cpu_phi2; - _sdram_cs = sdram_cs & cpu_phi2; - if (sdram_cs & ~cpu_rwb & ack) - next_teststate = S_1; - end - S_1: begin - if (~(sdram_cs & ~cpu_rwb)) - next_teststate = S_0; - end - endcase -end - -sdram_platform u0 ( - .clk_clk (clk_50), // clk.clk - .reset_reset_n (1'b1), // reset.reset_n - .ext_bus_address (cpu_addr), // ext_bus.address - .ext_bus_byte_enable (1'b1), // .byte_enable - .ext_bus_read (_sdram_cs & cpu_rwb), // .read - .ext_bus_write (write), // .write - .ext_bus_write_data (cpu_data_in), // .write_data - .ext_bus_acknowledge (ack), // .acknowledge - .ext_bus_read_data (sdram_data_out), // .read_data //SDRAM - .sdram_clk_clk(DRAM_CLK), //clk_sdram.clk - .sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr - .sdram_wire_ba(DRAM_BA), //.ba - .sdram_wire_cas_n(DRAM_CAS_N), //.cas_n - .sdram_wire_cke(DRAM_CKE), //.cke - .sdram_wire_cs_n(DRAM_CS_N), //.cs_n - .sdram_wire_dq(DRAM_DQ), //.dq - .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm - .sdram_wire_ras_n(DRAM_RAS_N), //.ras_n - .sdram_wire_we_n(DRAM_WE_N) //.we_n + .DRAM_CLK(DRAM_CLK), //clk_sdram.clk + .DRAM_ADDR(DRAM_ADDR), //sdram_wire.addr + .DRAM_BA(DRAM_BA), //.ba + .DRAM_CAS_N(DRAM_CAS_N), //.cas_n + .DRAM_CKE(DRAM_CKE), //.cke + .DRAM_CS_N(DRAM_CS_N), //.cs_n + .DRAM_DQ(DRAM_DQ), //.dq + .DRAM_UDQM(DRAM_UDQM), //.dqm + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), //.ras_n + .DRAM_WE_N(DRAM_WE_N) //.we_n ); - ram main_memory( .address(cpu_addr[14:0]), .clock(clk),