diff --git a/hw/fpga/SevenSeg.sv b/hw/fpga/SevenSeg.sv index 852b341..ff2179e 100644 --- a/hw/fpga/SevenSeg.sv +++ b/hw/fpga/SevenSeg.sv @@ -6,12 +6,12 @@ module SevenSeg( input [7:0] data, input cs, - input addr, + input [1:0] addr, - output logic [6:0] HEX0, HEX1, HEX2, HEX3 + output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 ); -logic [7:0] _data [2]; +logic [7:0] _data [3:0]; always_ff @(posedge clk) begin if (rst) @@ -21,12 +21,22 @@ always_ff @(posedge clk) begin end -logic [3:0] hex_4[3:0]; +logic [3:0] hex_4[5:0]; +assign {hex_4[5], hex_4[4]} = _data[2]; assign {hex_4[3], hex_4[2]} = _data[1]; assign {hex_4[1], hex_4[0]} = _data[0]; -HexDriver hex_drivers[3:0] (hex_4, {HEX3, HEX2, HEX1, HEX0}); +logic [6:0] _HEX0, _HEX1, _HEX2, _HEX3, _HEX4, _HEX5; + +HexDriver hex_drivers[5:0] (hex_4, {_HEX5, _HEX4, _HEX3, _HEX2, _HEX1, _HEX0}); + +assign HEX0 = _HEX0 | {7{~_data[3][0]}}; +assign HEX1 = _HEX1 | {7{~_data[3][1]}}; +assign HEX2 = _HEX2 | {7{~_data[3][2]}}; +assign HEX3 = _HEX3 | {7{~_data[3][3]}}; +assign HEX4 = _HEX4 | {7{~_data[3][4]}}; +assign HEX5 = _HEX5 | {7{~_data[3][5]}}; endmodule diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv index 65cdb45..1b4dd5e 100644 --- a/hw/fpga/addr_decode.sv +++ b/hw/fpga/addr_decode.sv @@ -7,6 +7,6 @@ module addr_decode( assign rom_cs = addr[15]; assign ram_cs = ~addr[15] && addr < 16'h7ff0; -assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff2; +assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4; endmodule diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv index 731443e..b552abb 100644 --- a/hw/fpga/hvl/cs_testbench.sv +++ b/hw/fpga/hvl/cs_testbench.sv @@ -26,7 +26,7 @@ initial begin : TEST_VECTORS else $error("Bad CS! addr=%4x should have ram_cs!", addr); end - if (i >= 16'h7ff0 && i < 16'h7ff2) begin + if (i >= 16'h7ff0 && i < 16'h7ff4) begin assert(hex_cs == '1) else $error("Bad CS! addr=%4x should have io_cs!", addr); diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index 5907dbf..7c3a514 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -200,181 +200,18 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50 set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "cpu_clk:cpu_clk|altpll:altpll_component|cpu_clk_altpll:auto_generated|wire_pll1_clk[0]~clkctrl" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "SevenSeg:segs|_data[0][0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "SevenSeg:segs|_data[0][1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "SevenSeg:segs|_data[0][2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "SevenSeg:segs|_data[0][3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "SevenSeg:segs|_data[0][4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "SevenSeg:segs|_data[0][5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "SevenSeg:segs|_data[0][6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "SevenSeg:segs|_data[0][7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "SevenSeg:segs|_data[1][0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "SevenSeg:segs|_data[1][1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "SevenSeg:segs|_data[1][2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "SevenSeg:segs|_data[1][3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "SevenSeg:segs|_data[1][4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "SevenSeg:segs|_data[1][5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "SevenSeg:segs|_data[1][6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "SevenSeg:segs|_data[1][7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "SevenSeg:segs|addr" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "SevenSeg:segs|clk" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "SevenSeg:segs|cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "SevenSeg:segs|rst" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "SevenSeg:segs|rw" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to cpu_addr[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to cpu_addr[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to cpu_addr[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to cpu_addr[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to cpu_addr[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to cpu_addr[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to cpu_addr[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to cpu_addr[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to cpu_addr[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to cpu_addr[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to cpu_addr[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to cpu_addr[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to cpu_addr[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to cpu_addr[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to cpu_addr[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to cpu_addr[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to cpu_data_in[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to cpu_data_in[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to cpu_data_in[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to cpu_data_in[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to cpu_data_in[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to cpu_data_in[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to cpu_data_in[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to cpu_data_in[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to cpu_data_out[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to cpu_data_out[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to cpu_data_out[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to cpu_data_out[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to cpu_data_out[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to cpu_data_out[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to cpu_data_out[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to cpu_data_out[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to cpu_phi2 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to cpu_rwb -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to cpu_sync -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to cpu_vpb -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to rst_n -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "SevenSeg:segs|_data[0][0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "SevenSeg:segs|_data[0][1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "SevenSeg:segs|_data[0][2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "SevenSeg:segs|_data[0][3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "SevenSeg:segs|_data[0][4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "SevenSeg:segs|_data[0][5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "SevenSeg:segs|_data[0][6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "SevenSeg:segs|_data[0][7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "SevenSeg:segs|_data[1][0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "SevenSeg:segs|_data[1][1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "SevenSeg:segs|_data[1][2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "SevenSeg:segs|_data[1][3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "SevenSeg:segs|_data[1][4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "SevenSeg:segs|_data[1][5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "SevenSeg:segs|_data[1][6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "SevenSeg:segs|_data[1][7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "SevenSeg:segs|addr" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "SevenSeg:segs|clk" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "SevenSeg:segs|cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "SevenSeg:segs|rst" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "SevenSeg:segs|rw" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to cpu_addr[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to cpu_addr[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to cpu_addr[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to cpu_addr[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to cpu_addr[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to cpu_addr[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to cpu_addr[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to cpu_addr[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to cpu_addr[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to cpu_addr[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to cpu_addr[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to cpu_addr[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to cpu_addr[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to cpu_addr[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to cpu_addr[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to cpu_addr[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to cpu_data_in[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to cpu_data_in[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to cpu_data_in[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to cpu_data_in[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to cpu_data_in[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to cpu_data_in[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to cpu_data_in[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to cpu_data_in[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to cpu_data_out[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to cpu_data_out[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to cpu_data_out[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to cpu_data_out[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to cpu_data_out[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to cpu_data_out[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to cpu_data_out[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to cpu_data_out[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to cpu_phi2 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to cpu_rwb -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to cpu_sync -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to cpu_vpb -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to rst_n -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=58" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=58" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=58" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=198" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 6690d3c..1b61440 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -20,7 +20,7 @@ module super6502( output logic cpu_be, output logic cpu_nmib, - output logic [6:0] HEX0, HEX1, HEX2, HEX3 + output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 ); logic rst; @@ -99,8 +99,8 @@ SevenSeg segs( .rw(cpu_rwb), .data(cpu_data_in), .cs(hex_cs), - .addr(cpu_addr[0]), - .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), + .addr(cpu_addr[1:0]), + .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5) ); diff --git a/sw/io.inc65 b/sw/io.inc65 index 8f254ac..4bf4736 100644 --- a/sw/io.inc65 +++ b/sw/io.inc65 @@ -1 +1 @@ -BB_SPI_BASE = $7ff0 +SEVEN_SEG = $7ff0 diff --git a/sw/main.c b/sw/main.c index a09a475..c7a5217 100644 --- a/sw/main.c +++ b/sw/main.c @@ -1,11 +1,10 @@ -#define SEVEN_SEG 0x7ff0 - #include -int main() { - uint16_t* seven_seg; - seven_seg = (uint16_t*)SEVEN_SEG; +#include "sevenseg.h" - *seven_seg = 0xbabe; +int main() { + hex_enable(0x3f); + hex_set_24(0xabcdef); + while(1); return 0; } diff --git a/sw/sevenseg.h b/sw/sevenseg.h new file mode 100644 index 0000000..a2b2175 --- /dev/null +++ b/sw/sevenseg.h @@ -0,0 +1,12 @@ +#ifndef _SEVEN_SEG +#define _SEVEN_SEG + +#include + +uint8_t hex_set_8(uint8_t val, uint8_t idx); +uint8_t hex_set_16(uint16_t val); +uint8_t hex_set_24(uint32_t val); + +void hex_enable(uint8_t mask); + +#endif \ No newline at end of file diff --git a/sw/sevenseg.s b/sw/sevenseg.s new file mode 100644 index 0000000..6b9efc6 --- /dev/null +++ b/sw/sevenseg.s @@ -0,0 +1,55 @@ +.include "io.inc65" + +.importzp sp, sreg + +.export _hex_set_8 +.export _hex_set_16 +.export _hex_set_24 +.export _hex_enable + +.autoimport on + +.code + +; @in A: idx Stack[0]: val +; @out A: 0 for success, 1 for failure. +; Sets one of the 3 pairs of hex digits. +_hex_set_8: + phx + cmp #$3 ; If idx >= 3 then fail + bcc @1 + plx + lda #$1 + rts +@1: tax ; Move idx into x + jsr popa ; put val into a + sta SEVEN_SEG,x ; write to val + lda #$0 + plx + rts + +; @in A/X: val +; @out A: 0 for success, 1 for failure +; Sets the low 2 pairs of hex digits +_hex_set_16: + sta SEVEN_SEG + stx SEVEN_SEG+1 + lda #$0 + rts + +; @in A/X/sreg: val +; @out A: 0 for success, 1 for failure +; Sets the 3 pairs of hex digits for a 24 bit value +_hex_set_24: + sta SEVEN_SEG + stx SEVEN_SEG+1 + lda sreg + sta SEVEN_SEG+2 + lda #$0 + rts + +; @in A: mask +; Set the mask for seven seg enables +_hex_enable: + sta SEVEN_SEG+3 + rts \ No newline at end of file diff --git a/sw/tests/test_main.c b/sw/tests/test_main.c index 0356d35..2f32592 100644 --- a/sw/tests/test_main.c +++ b/sw/tests/test_main.c @@ -1,7 +1,61 @@ #include +#include "sevenseg.h" + int main(void) { - printf("No test to run!\n"); - return 0; + int retval = 0; + + int i; + + printf("\nStarting tests...\n\n"); + + printf("Testing hex_set_8...\n"); + for (i = 0; i < 3; i++) { + if (hex_set_8(i+1, i)) { + printf("Failed to write to idx %d!\n", i); + retval++; + } + if (*(uint8_t*)0x7ff0+i != i+1) { + printf("Incorrect value at idx %d!\n", i); + retval++; + } + } + + if (!hex_set_8(0xab, 3)) { + printf("Writing to idx 3 should fail!\n"); + retval++; + } + printf("Done!\n\n"); + + printf("Testing hex_set_16...\n"); + if (hex_set_16(0xabcd)){ + printf("Failed to write!\n"); + } + if (*(uint16_t*)0x7ff0 != 0xabcd) { + printf("Incorrect value!\n", i); + retval++; + } + printf("Done!\n\n"); + + printf("Testing hex_set_24...\n"); + if (hex_set_24(0xabcdef)){ + printf("Failed to write!\n"); + } + if (*(uint16_t*)0x7ff0 != 0xcdef && *(uint8_t*)0x7ff2 != 0xab) { + printf("Incorrect value!\n", i); + retval++; + } + printf("Done!\n\n"); + + printf("Testing hex_enable...\n"); + hex_enable(0xa5); + if (*(uint8_t*)0x7ff3 != 0xa5) { + printf("Incorrect value!\n", i); + retval++; + } + printf("Done!\n\n"); + + + return retval != 0; } \ No newline at end of file