From 4612acbc4a27df251d8a12148ba7b327bfdc4b69 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 9 Sep 2024 22:02:39 -0700 Subject: [PATCH] Synthesis 1 --- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 94 ++++++++----------- .../network_processor/src/tcp_dest_decap.sv | 9 +- .../sub/network_processor/src/tcp_rx_ctrl.sv | 2 + hw/super6502_fpga/super6502_fpga.xml | 21 ++++- 4 files changed, 64 insertions(+), 62 deletions(-) diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index e95dfd4..2c61004 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -211,23 +211,8 @@ logic sd_controller_dma_RREADY; logic [DATA_WIDTH-1:0] sd_controller_dma_RDATA; logic [1:0] sd_controller_dma_RRESP; -logic ntw_reg_AWVALID; -logic ntw_reg_AWREADY; -logic [ADDR_WIDTH-1:0] ntw_reg_AWADDR; -logic ntw_reg_WVALID; -logic ntw_reg_WREADY; -logic [DATA_WIDTH-1:0] ntw_reg_WDATA; -logic [DATA_WIDTH/8-1:0] ntw_reg_WSTRB; -logic ntw_reg_BVALID; -logic ntw_reg_BREADY; -logic [1:0] ntw_reg_BRESP; -logic ntw_reg_ARVALID; -logic ntw_reg_ARREADY; -logic [ADDR_WIDTH-1:0] ntw_reg_ARADDR; -logic ntw_reg_RVALID; -logic ntw_reg_RREADY; -logic [DATA_WIDTH-1:0] ntw_reg_RDATA; -logic [1:0] ntw_reg_RRESP; +axil_intf ntw_reg(); +axil_intf ntw_dma(); cpu_wrapper u_cpu_wrapper_0( @@ -305,23 +290,23 @@ axilxbar #( .S_AXI_BRESP ({cpu0_BRESP, sd_controller_dma_BRESP }), .S_AXI_BVALID ({cpu0_BVALID, sd_controller_dma_BVALID }), .S_AXI_BREADY ({cpu0_BREADY, sd_controller_dma_BREADY }), - .M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR, ntw_reg_ARADDR }), - .M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID, ntw_reg_ARVALID }), - .M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY, ntw_reg_ARREADY }), - .M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA, ntw_reg_RDATA }), - .M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP, ntw_reg_RRESP }), - .M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID, ntw_reg_RVALID }), - .M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY, ntw_reg_RREADY }), - .M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR, ntw_reg_AWADDR }), - .M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID, ntw_reg_AWVALID }), - .M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY, ntw_reg_AWREADY }), - .M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA, ntw_reg_WDATA }), - .M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID, ntw_reg_WVALID }), - .M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY, ntw_reg_WREADY }), - .M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB, ntw_reg_WSTRB }), - .M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP, ntw_reg_BRESP }), - .M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID, ntw_reg_BVALID }), - .M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY, ntw_reg_BREADY }) + .M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR, ntw_reg.araddr }), + .M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID, ntw_reg.arvalid }), + .M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY, ntw_reg.arready }), + .M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA, ntw_reg.rdata }), + .M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP, ntw_reg.rresp }), + .M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID, ntw_reg.rvalid }), + .M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY, ntw_reg.rready }), + .M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR, ntw_reg.awaddr }), + .M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID, ntw_reg.awvalid }), + .M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY, ntw_reg.awready }), + .M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA, ntw_reg.wdata }), + .M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID, ntw_reg.wvalid }), + .M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY, ntw_reg.wready }), + .M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB, ntw_reg.wstrb }), + .M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP, ntw_reg.bresp }), + .M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID, ntw_reg.bvalid }), + .M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY, ntw_reg.bready }) ); @@ -524,28 +509,27 @@ sd_controller_wrapper #( network_processor #( .NUM_TCP(8) ) u_network_processor ( - .i_clk (i_sysclk), - .i_rst (~master_resetn), + .i_clk (i_sysclk), + .i_rst (~master_resetn), - .s_reg_axil_awready (ntw_reg_AWREADY), - .s_reg_axil_awvalid (ntw_reg_AWVALID), - .s_reg_axil_awaddr (ntw_reg_AWADDR), - .s_reg_axil_awprot (ntw_reg_AWPROT), - .s_reg_axil_wready (ntw_reg_WREADY), - .s_reg_axil_wvalid (ntw_reg_WVALID), - .s_reg_axil_wdata (ntw_reg_WDATA), - .s_reg_axil_wstrb (ntw_reg_WSTRB), - .s_reg_axil_bready (ntw_reg_BREADY), - .s_reg_axil_bvalid (ntw_reg_BVALID), - .s_reg_axil_bresp (ntw_reg_BRESP), - .s_reg_axil_arready (ntw_reg_ARREADY), - .s_reg_axil_arvalid (ntw_reg_ARVALID), - .s_reg_axil_araddr (ntw_reg_ARADDR), - .s_reg_axil_arprot (ntw_reg_ARPROT), - .s_reg_axil_rready (ntw_reg_RREADY), - .s_reg_axil_rvalid (ntw_reg_RVALID), - .s_reg_axil_rdata (ntw_reg_RDATA), - .s_reg_axil_rresp (ntw_reg_RRESP) + .s_reg_axil (ntw_reg), + .m_dma_axil (ntw_dma), + + .mii_rx_clk (mii_rx_clk), + .mii_rxd (mii_rxd), + .mii_rx_dv (mii_rx_dv), + .mii_rx_er (mii_rx_er), + .mii_tx_clk (mii_tx_clk), + .mii_txd (mii_txd), + .mii_tx_en (mii_tx_en), + .mii_tx_er (mii_tx_er), + + .i_Mdi (i_Mdi), + .o_Mdo (o_Mdo), + .o_MdoEn (o_MdoEn), + .o_Mdc (o_Mdc), + + .phy_rstn (phy_rstn) ); endmodule diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv index b67fe9f..48a8406 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp_dest_decap.sv @@ -1,7 +1,7 @@ module tcp_dest_decap ( input i_clk, input i_rst, - + ip_intf.SLAVE s_ip, ip_intf.MASTER m_ip, @@ -15,6 +15,8 @@ logic [31:0] pipe, pipe_next; logic [3:0] pipe_valid, pipe_valid_next; logic [3:0] pipe_last, pipe_last_next; +logic valid; + enum logic [1:0] {PORTS, PASSTHROUGH} state, state_next; logic [1:0] counter, counter_next; @@ -25,6 +27,7 @@ assign m_ip.eth_src_mac = '0; assign m_ip.eth_dest_mac = '0; assign m_ip.eth_type = '0; +assign o_tcp_dest_valid = valid; assign o_tcp_dest = tcp_dest; skidbuffer #( @@ -100,7 +103,7 @@ always_comb begin case (state) PORTS: begin s_ip.ip_payload_axis_tready = 1; - o_tcp_dest_valid = '0; + valid = '0; if (s_ip.ip_payload_axis_tvalid) begin counter_next = counter + 1; @@ -124,7 +127,7 @@ always_comb begin m_ip.ip_payload_axis_tlast = pipe_last[3]; m_ip.ip_payload_axis_tdata = pipe[31:24]; - o_tcp_dest_valid = '1; + valid = '1; end endcase end diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv index c1c642e..c8ac1d9 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv @@ -1,3 +1,5 @@ +import tcp_pkg::*; + module tcp_rx_ctrl ( input wire i_clk, input wire i_rst, diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 9138c2a..8023c3f 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,4 +1,4 @@ - + @@ -45,11 +45,8 @@ - - - @@ -190,6 +187,22 @@ + + + + + + + + + + + + + + + +