diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 0b9945e..227ae42 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -8,34 +8,34 @@ logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
 
 // clk_100
 initial begin
-	r_sysclk <= '1;
-	forever begin
-		#5 r_sysclk <= ~r_sysclk;
-	end
+    r_sysclk <= '1;
+    forever begin
+        #5 r_sysclk <= ~r_sysclk;
+    end
 end
 
 // clk_200
 initial begin
-	r_sdrclk <= '1;
-	forever begin
-		#2.5 r_sdrclk <= ~r_sdrclk;
-	end
+    r_sdrclk <= '1;
+    forever begin
+        #2.5 r_sdrclk <= ~r_sdrclk;
+    end
 end
 
 // clk_50
 initial begin
-	r_clk_50 <= '1;
-	forever begin
-		#10 r_clk_50 <= ~r_clk_50;
-	end
+    r_clk_50 <= '1;
+    forever begin
+        #10 r_clk_50 <= ~r_clk_50;
+    end
 end
 
 // clk_2
 initial begin
-	r_clk_2 <= '1;
-	forever begin
-		#250 r_clk_2 <= ~r_clk_2;
-	end
+    r_clk_2 <= '1;
+    forever begin
+        #250 r_clk_2 <= ~r_clk_2;
+    end
 end
 
 initial begin
@@ -46,11 +46,11 @@ end
 logic button_reset;
 
 initial begin
-	button_reset <= '0;
-	repeat(10) @(r_clk_2);
-	button_reset <= '1;
-	repeat(20000) @(r_clk_2);
-	$finish();
+    button_reset <= '0;
+    repeat(10) @(r_clk_2);
+    button_reset <= '1;
+    repeat(20000) @(r_clk_2);
+    $finish();
 end
 
 logic w_cpu_reset;
@@ -62,53 +62,55 @@ logic w_cpu_phi2;
 
 //TODO: this
 cpu_65c02 u_cpu(
-	.phi2(w_cpu_phi2),
-	.reset(~w_cpu_reset),
-	.AB(w_cpu_addr),
-	.RDY(w_cpu_rdy),
-	.IRQ('0),
-	.NMI('0),
-	.DI_s1(w_cpu_data_from_dut),
-	.DO(w_cpu_data_from_cpu),
-	.WE(w_cpu_we)
+    .phi2(w_cpu_phi2),
+    .reset(~w_cpu_reset),
+    .AB(w_cpu_addr),
+    .RDY(w_cpu_rdy),
+    .IRQ('0),
+    .NMI('0),
+    .DI_s1(w_cpu_data_from_dut),
+    .DO(w_cpu_data_from_cpu),
+    .WE(w_cpu_we)
+);
+
+logic w_dut_uart_rx, w_dut_uart_tx;
+
+sim_uart u_sim_uart(
+    .clk_50(r_clk_50),
+    .reset(~w_cpu_reset),
+    .rx_i(w_dut_uart_tx),
+    .tx_o(w_dut_uart_rx)
 );
 
 
-// Having the super6502 causes an infinite loop,
-// but just the rom works. Need to whittle down
-// which block is causing it.
-// rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
-//     .addr(w_cpu_addr[11:0]),
-//     .clk(r_clk_2),
-//     .data(w_cpu_data_from_dut)
-// );
-
-//TODO: also this
 super6502 u_dut(
-	.i_sysclk(r_sysclk),
-	.i_sdrclk(r_sdrclk),
-	.i_tACclk(~r_sdrclk),
-	.clk_50(r_clk_50),
-	.clk_2(r_clk_2),
-	.button_reset(button_reset),
-	.cpu_resb(w_cpu_reset),
-	.cpu_addr(w_cpu_addr),
-	.cpu_data_out(w_cpu_data_from_dut),
-	.cpu_data_in(w_cpu_data_from_cpu),
-	.cpu_rwb(~w_cpu_we),
-	.cpu_rdy(w_cpu_rdy),
-	.cpu_phi2(w_cpu_phi2),
+    .i_sysclk(r_sysclk),
+    .i_sdrclk(r_sdrclk),
+    .i_tACclk(~r_sdrclk),
+    .clk_50(r_clk_50),
+    .clk_2(r_clk_2),
+    .button_reset(button_reset),
+    .cpu_resb(w_cpu_reset),
+    .cpu_addr(w_cpu_addr),
+    .cpu_data_out(w_cpu_data_from_dut),
+    .cpu_data_in(w_cpu_data_from_cpu),
+    .cpu_rwb(~w_cpu_we),
+    .cpu_rdy(w_cpu_rdy),
+    .cpu_phi2(w_cpu_phi2),
 
-	.o_sdr_CKE(w_sdr_CKE),
-	.o_sdr_n_CS(w_sdr_n_CS),
-	.o_sdr_n_WE(w_sdr_n_WE),
-	.o_sdr_n_RAS(w_sdr_n_RAS),
-	.o_sdr_n_CAS(w_sdr_n_CAS),
-	.o_sdr_BA(w_sdr_BA),
-	.o_sdr_ADDR(w_sdr_ADDR),
-	.i_sdr_DATA(w_sdr_DQ),
-	.o_sdr_DATA(w_sdr_DATA),
-	.o_sdr_DATA_oe(w_sdr_DATA_oe),
+    .uart_rx(w_dut_uart_rx),
+    .uart_tx(w_dut_uart_tx),
+
+    .o_sdr_CKE(w_sdr_CKE),
+    .o_sdr_n_CS(w_sdr_n_CS),
+    .o_sdr_n_WE(w_sdr_n_WE),
+    .o_sdr_n_RAS(w_sdr_n_RAS),
+    .o_sdr_n_CAS(w_sdr_n_CAS),
+    .o_sdr_BA(w_sdr_BA),
+    .o_sdr_ADDR(w_sdr_ADDR),
+    .i_sdr_DATA(w_sdr_DQ),
+    .o_sdr_DATA(w_sdr_DATA),
+    .o_sdr_DATA_oe(w_sdr_DATA_oe),
     .o_sdr_DQM(w_sdr_DQM)
 );
 
@@ -126,29 +128,28 @@ wire	[DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DQ;
 
 genvar i, j;
 generate
-	for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
-	begin: DQ_map
-		assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i])?
-									w_sdr_DATA[i]:1'bz;
-	end
+    for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
+    begin: DQ_map
+        assign	w_sdr_DQ[i]	=	(w_sdr_DATA_oe[i])?
+                                    w_sdr_DATA[i]:1'bz;
+    end
 
-	for (j=0; j<DQ_GROUP; j=j+1)
-	begin : mem_inst
+    for (j=0; j<DQ_GROUP; j=j+1)
+    begin : mem_inst
         generic_sdr inst_sdr
         (
-        	.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
-        	.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
-        	.Ba(w_sdr_BA[BA_WIDTH-1:0]),
-        	.Clk(~r_sdrclk),
-        	.Cke(w_sdr_CKE),
-        	.Cs_n(w_sdr_n_CS),
-        	.Ras_n(w_sdr_n_RAS),
-        	.Cas_n(w_sdr_n_CAS),
-        	.We_n(w_sdr_n_WE),
-        	.Dqm(w_sdr_DQM[j])
+            .Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
+            .Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
+            .Ba(w_sdr_BA[BA_WIDTH-1:0]),
+            .Clk(~r_sdrclk),
+            .Cke(w_sdr_CKE),
+            .Cs_n(w_sdr_n_CS),
+            .Ras_n(w_sdr_n_RAS),
+            .Cas_n(w_sdr_n_CAS),
+            .We_n(w_sdr_n_WE),
+            .Dqm(w_sdr_DQM[j])
         );
     end
 endgenerate
 
-
 endmodule
\ No newline at end of file
diff --git a/hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv b/hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv
new file mode 100644
index 0000000..f7526ce
--- /dev/null
+++ b/hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv
@@ -0,0 +1,43 @@
+module sim_uart(
+    input clk,
+    input clk_50,
+    input reset,
+
+    input [7:0] i_data,
+
+    input rx_i,
+    output tx_o
+);
+
+logic tx_busy, rx_busy;
+
+logic rx_data_valid, rx_error, rx_parity_error;
+logic baud_x16_ce;
+
+logic tx_en;
+
+logic [7:0] tx_data, rx_data;
+
+uart u_uart(
+    .tx_o ( tx_o ),
+    .rx_i ( rx_i ),
+    .tx_busy ( tx_busy ),
+    .rx_data ( rx_data ),
+    .rx_data_valid ( rx_data_valid ),
+    .rx_error ( rx_error ),
+    .rx_parity_error ( rx_parity_error ),
+    .rx_busy ( rx_busy ),
+    .baud_x16_ce ( baud_x16_ce ),
+    .clk ( clk_50 ),
+    .reset ( reset ),
+    .tx_data ( tx_data ),
+    .baud_rate ( baud_rate ),
+    .tx_en ( tx_en )
+);
+
+always @(posedge baud_x16_ce) begin
+    if (rx_data_valid)
+        $display("UART: %c", rx_data);
+end
+
+endmodule