diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list
index 0ef340c..59e3c2a 100644
--- a/hw/super6502_fpga/sources.list
+++ b/hw/super6502_fpga/sources.list
@@ -12,13 +12,4 @@ src/sub/rtl-common/src/rtl/ff_cdc.sv
 src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
 src/sub/rtl-common/src/rtl/sync_fifo.sv
 src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv
-ip/sdram_controller/sdram_controller.v
-src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv
-src/sub/sd_controller/src/regs/sd_controller_regs.sv
-src/sub/sd_controller/src/crc7.sv
-src/sub/sd_controller/src/crc16.sv
-src/sub/sd_controller/src/sd_command.sv
-src/sub/sd_controller/src/sd_control.sv
-src/sub/sd_controller/src/sd_controller_top.sv
-src/sub/sd_controller/src/sd_data.sv
-src/sub/sd_controller/src/sd_dma.sv
\ No newline at end of file
+ip/sdram_controller/sdram_controller.v
\ No newline at end of file
diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
index a1fae5c..0e4b29a 100644
--- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
+++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv
@@ -464,49 +464,4 @@ axi4_lite_to_apb4 u_sd_axi_apb_converter (
     .m_apb_pslverr(sd_controller_apb_pslverr)
 );
 
-sd_controller_top u_sd_controller (
-    .clk(i_sysclk),
-    .rst(~master_reset),
-
-    .s_apb_psel(sd_controller_apb_psel),
-    .s_apb_penable(sd_controller_apb_penable),
-    .s_apb_pwrite(sd_controller_apb_pwrite),
-    .s_apb_pprot(sd_controller_apb_pprot),
-    .s_apb_paddr(sd_controller_apb_paddr[5:0]),
-    .s_apb_pwdata(sd_controller_apb_pwdata),
-    .s_apb_pstrb(sd_controller_apb_pstrb),
-    .s_apb_pready(sd_controller_apb_pready),
-    .s_apb_prdata(sd_controller_apb_prdata),
-    .s_apb_pslverr(sd_controller_apb_pslverr),
-
-    .o_AWVALID  (sd_controller_dma_AWVALID),
-    .i_AWREADY  (sd_controller_dma_AWREADY),
-    .o_AWADDR   (sd_controller_dma_AWADDR),
-    .o_WVALID   (sd_controller_dma_WVALID),
-    .i_WREADY   (sd_controller_dma_WREADY),
-    .o_WDATA    (sd_controller_dma_WDATA),
-    .o_WSTRB    (sd_controller_dma_WSTRB),
-    .i_BVALID   (sd_controller_dma_BVALID),
-    .o_BREADY   (sd_controller_dma_BREADY),
-    .i_BRESP    (sd_controller_dma_BRESP),
-    .o_ARVALID  (sd_controller_dma_ARVALID),
-    .i_ARREADY  (sd_controller_dma_ARREADY),
-    .o_ARADDR   (sd_controller_dma_ARADDR),
-    .i_RVALID   (sd_controller_dma_RVALID),
-    .o_RREADY   (sd_controller_dma_RREADY),
-    .i_RDATA    (sd_controller_dma_RDATA),
-    .i_RRESP    (sd_controller_dma_RRESP),
-
-    
-
-    .i_sd_cmd(i_sd_cmd),
-    .o_sd_cmd(o_sd_cmd),
-    .o_sd_cmd_oe(o_sd_cmd_oe),
-    .o_sd_clk(o_sd_clk),
-
-    .i_sd_dat(i_sd_dat),
-    .o_sd_dat(o_sd_dat),
-    .o_sd_dat_oe(o_sd_dat_oe)
-);
-
 endmodule
\ No newline at end of file
diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml
index cb3545b..efb40f1 100644
--- a/hw/super6502_fpga/super6502_fpga.xml
+++ b/hw/super6502_fpga/super6502_fpga.xml
@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 17 2024 10:14:03 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Tue Jul 16 2024 12:02:55 AM" location="/cluster/projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />
@@ -17,15 +17,6 @@
         <efx:design_file name="src/sub/axi_crossbar/src/rtl/axi_crossbar.sv" version="default" library="default" />
         <efx:design_file name="src/sub/axi_crossbar/src/rtl/rr_scheduler.sv" version="default" library="default" />
         <efx:design_file name="src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/crc16.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/crc7.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/sd_control.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/sd_controller_top.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/sd_command.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/sd_dma.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv" version="default" library="default" />
-        <efx:design_file name="src/sub/sd_controller/src/sd_data.sv" version="default" library="default" />
         <efx:design_file name="src/sub/rtl-common/src/rtl/async_fifo.sv" version="default" library="default" />
         <efx:top_vhdl_arch name="" />
     </efx:design_info>
@@ -72,9 +63,9 @@
         <efx:param name="work_dir" value="work_pnr" value_type="e_string" />
         <efx:param name="verbose" value="off" value_type="e_bool" />
         <efx:param name="load_delaym" value="on" value_type="e_bool" />
-        <efx:param name="optimization_level" value="NULL" value_type="e_option" />
+        <efx:param name="optimization_level" value="TIMING_3" value_type="e_option" />
         <efx:param name="seed" value="1" value_type="e_integer" />
-        <efx:param name="placer_effort_level" value="2" value_type="e_option" />
+        <efx:param name="placer_effort_level" value="5" value_type="e_option" />
         <efx:param name="max_threads" value="-1" value_type="e_integer" />
     </efx:place_and_route>
     <efx:bitstream_generation tool_name="efx_pgm">