From 4f8e63f463d028b6158ce435f9b7285d59b2a21a Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Fri, 6 Jan 2023 10:28:08 -0500 Subject: [PATCH] Update sdram controller with new Efinity version For some reason the old one did not want to open in the new version. Even though the version of the IP is the same, something about it being made with the old Efinity version made it mad. I just deleted it and made it again with the same settings and now it lets me open and configure it. --- .../ip/sdram_controller/sdram_controller.v | 50 +++++++++---------- .../sdram_controller_define.vh | 48 +++++++++--------- .../ip/sdram_controller/settings.json | 14 +++--- 3 files changed, 56 insertions(+), 56 deletions(-) diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v index 290e4d6..4ece735 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v @@ -1,6 +1,6 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.1.226 +// Version: 2022.2.322 // IP Version: 1.6 // ============================================================================= @@ -43,7 +43,7 @@ // //////////////////////////////////////////////////////////////////////////////// -`define IP_UUID _1a076fc510c34dc9a60c0ede33930d9f +`define IP_UUID _08775b1d2de94ebcb82f5350820af2e3 `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module sdram_controller ( @@ -93,40 +93,40 @@ output o_dbg_tRCD_done ); `IP_MODULE_NAME(efx_sdram_controller) #( .fSYS_MHz (100), -.fCK_MHz (200), +.fCK_MHz (200), .tIORT_u (2), +.CL (3), .BL (1), .DDIO_TYPE ("SOFT"), -.DQ_WIDTH (8), +.DQ_WIDTH (8), .DQ_GROUP (2), -.BA_WIDTH (2), -.ROW_WIDTH (13), -.COL_WIDTH (9), -.tPWRUP (200000), -.tRAS (44), -.tRC (66), +.BA_WIDTH (2), +.ROW_WIDTH (13), +.COL_WIDTH (9), +.tPWRUP (200000), +.tRAS (44), +.tRAS_MAX (120000), +.tRC (66), .tRCD (20), -.tREF (64000000), +.tREF (64000000), +.tRFC (66), +.tRP (20), .tWR (2), .tMRD (2), -.tRFC (66), -.tRAS_MAX (120000), -.DATA_RATE (2), -.AXI_ARADDR_WIDTH (24), .SDRAM_MODE ("Native"), -.AXI_BUSER_WIDTH (2), -.AXI_BID_WIDTH (4), -.AXI_AWUSER_WIDTH (2), -.AXI_AWID_WIDTH (4), +.DATA_RATE (2), .AXI_AWADDR_WIDTH (24), -.AXI_RDATA_WIDTH (32), -.AXI_WUSER_WIDTH (2), .AXI_WDATA_WIDTH (32), -.AXI_RUSER_WIDTH (3), -.AXI_ARUSER_WIDTH (3), +.AXI_ARADDR_WIDTH (24), +.AXI_RDATA_WIDTH (32), +.AXI_AWID_WIDTH (4), +.AXI_AWUSER_WIDTH (2), +.AXI_WUSER_WIDTH (2), +.AXI_BID_WIDTH (4), +.AXI_BUSER_WIDTH (2), .AXI_ARID_WIDTH (4), -.tRP (20), -.CL (3) +.AXI_ARUSER_WIDTH (3), +.AXI_RUSER_WIDTH (3) ) u_efx_sdram_controller( .i_we ( i_we ), .i_sysclk ( i_sysclk ), diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh index 82a8008..9c5f846 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh @@ -1,6 +1,6 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.1.226 +// Version: 2022.2.322 // IP Version: 1.6 // ============================================================================= @@ -44,37 +44,37 @@ //////////////////////////////////////////////////////////////////////////////// localparam fSYS_MHz = 100; -localparam fCK_MHz = 200; +localparam fCK_MHz = 200; localparam tIORT_u = 2; +localparam CL = 3; localparam BL = 1; localparam DDIO_TYPE = "SOFT"; -localparam DQ_WIDTH = 8; +localparam DQ_WIDTH = 8; localparam DQ_GROUP = 2; -localparam BA_WIDTH = 2; -localparam ROW_WIDTH = 13; -localparam COL_WIDTH = 9; -localparam tPWRUP = 200000; -localparam tRAS = 44; -localparam tRC = 66; +localparam BA_WIDTH = 2; +localparam ROW_WIDTH = 13; +localparam COL_WIDTH = 9; +localparam tPWRUP = 200000; +localparam tRAS = 44; +localparam tRAS_MAX = 120000; +localparam tRC = 66; localparam tRCD = 20; -localparam tREF = 64000000; +localparam tREF = 64000000; +localparam tRFC = 66; +localparam tRP = 20; localparam tWR = 2; localparam tMRD = 2; -localparam tRFC = 66; -localparam tRAS_MAX = 120000; -localparam DATA_RATE = 2; -localparam AXI_ARADDR_WIDTH = 24; localparam SDRAM_MODE = "Native"; -localparam AXI_BUSER_WIDTH = 2; -localparam AXI_BID_WIDTH = 4; -localparam AXI_AWUSER_WIDTH = 2; -localparam AXI_AWID_WIDTH = 4; +localparam DATA_RATE = 2; localparam AXI_AWADDR_WIDTH = 24; -localparam AXI_RDATA_WIDTH = 32; -localparam AXI_WUSER_WIDTH = 2; localparam AXI_WDATA_WIDTH = 32; -localparam AXI_RUSER_WIDTH = 3; -localparam AXI_ARUSER_WIDTH = 3; +localparam AXI_ARADDR_WIDTH = 24; +localparam AXI_RDATA_WIDTH = 32; +localparam AXI_AWID_WIDTH = 4; +localparam AXI_AWUSER_WIDTH = 2; +localparam AXI_WUSER_WIDTH = 2; +localparam AXI_BID_WIDTH = 4; +localparam AXI_BUSER_WIDTH = 2; localparam AXI_ARID_WIDTH = 4; -localparam tRP = 20; -localparam CL = 3; +localparam AXI_ARUSER_WIDTH = 3; +localparam AXI_RUSER_WIDTH = 3; diff --git a/hw/efinix_fpga/ip/sdram_controller/settings.json b/hw/efinix_fpga/ip/sdram_controller/settings.json index e43a50e..42643e4 100644 --- a/hw/efinix_fpga/ip/sdram_controller/settings.json +++ b/hw/efinix_fpga/ip/sdram_controller/settings.json @@ -26,19 +26,19 @@ "tRC": "66", "tRCD": "20", "tREF": "64000000", - "tRFC ": "66", + "tRFC": "66", "tRP": "20", "SDRAM_MODE": "0", "DATA_RATE": "2" }, "output": { - "external_source": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v", + "external_source_source": [ "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd" + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v" ] }, - "sw_version": "2022.1.226", - "generated_date": "2022-12-22T03:56:49.168890" + "sw_version": "2022.2.322", + "generated_date": "2023-01-06T15:14:53.619359" } \ No newline at end of file