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Update cs_testbench.sv

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Add uart_cs and fix error messages
This commit is contained in:
Byron Lathi
2022-03-14 10:56:10 -05:00
parent a671fda51c
commit 4fb73f8e97
1 changed files with 8 additions and 2 deletions
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10
hw/fpga/hvl/cs_testbench.sv
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@@ -8,8 +8,9 @@ logic [15:0] addr;
logic ram_cs; logic ram_cs;
logic rom_cs; logic rom_cs;
logic hex_cs; logic hex_cs;
logic uart_cs;
int cs_count = ram_cs + rom_cs + hex_cs; int cs_count = ram_cs + rom_cs + hex_cs + uart_cs;
addr_decode dut(.*); addr_decode dut(.*);
@@ -29,7 +30,12 @@ initial begin : TEST_VECTORS
if (i >= 16'h7ff0 && i < 16'h7ff4) begin if (i >= 16'h7ff0 && i < 16'h7ff4) begin
assert(hex_cs == '1) assert(hex_cs == '1)
else else
$error("Bad CS! addr=%4x should have io_cs!", addr); $error("Bad CS! addr=%4x should have hex_cs!", addr);
end
if (i >= 16'h7ff4 && i < 16'6) begin
assert(uart_cs == '1)
else
$error("Bad CS! addr=%4x should have uart_cs!", addr);
end end
if (i >= 2**15) begin if (i >= 2**15) begin
assert(rom_cs == '1) assert(rom_cs == '1)