diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..722d5e7 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +.vscode diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index 0cbf8a7..0000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "files.associations": { - "conio.h": "c" - } -} \ No newline at end of file diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index 48320cd..bde918f 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -8,7 +8,7 @@ module addr_decode output o_multiplier_cs, output o_divider_cs, output o_uart_cs, - output o_sdcard_cs, + output o_spi_cs, output o_sdram_cs ); @@ -17,7 +17,7 @@ assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb; assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7; assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef; assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7; -assign o_sdcard_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdf; +assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb; assign o_leds_cs = i_addr == 16'hefff; assign o_sdram_cs = i_addr < 16'h8000; diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index e3e4271..f161bb2 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,12 +3,12 @@ { "name": "la0", "type": "la", - "uuid": "839a8cb8163a4829a5cc15adcbae907b", + "uuid": "fc5ad0b7db9846e2b64719110e7975d8", "trigin_en": false, "trigout_en": false, "auto_inserted": true, "capture_control": false, - "data_depth": 4096, + "data_depth": 16384, "input_pipeline": 1, "probes": [ { @@ -36,123 +36,33 @@ "width": 16, "probe_type": 1 }, - { - "name": "cpu_nmib", - "width": 1, - "probe_type": 1 - }, - { - "name": "cpu_irqb", - "width": 1, - "probe_type": 1 - }, - { - "name": "cpu_data_out", - "width": 8, - "probe_type": 1 - }, { "name": "cpu_phi2", "width": 1, "probe_type": 1 }, { - "name": "u_sdram_adapter/o_dbg_wr_ack", + "name": "spi_clk", "width": 1, "probe_type": 1 }, { - "name": "u_sdram_adapter/next_counter", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/o_data", - "width": 8, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/next_state", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_data_i", - "width": 32, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_rwb", + "name": "spi_mosi", "width": 1, "probe_type": 1 }, { - "name": "u_sdram_adapter/w_addr", - "width": 24, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_data_o", - "width": 32, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/i_cs", + "name": "sd_cs", "width": 1, "probe_type": 1 }, { - "name": "u_sdram_adapter/counter", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/state", - "width": 2, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_last", + "name": "spi_miso", "width": 1, "probe_type": 1 }, { - "name": "u_sdram_adapter/w_data_valid", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_wr_ack", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_read", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_write", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_rd_ack", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/w_rd_valid", - "width": 1, - "probe_type": 1 - }, - { - "name": "u_sdram_adapter/o_dbg_ref_req", - "width": 1, - "probe_type": 1 - }, - { - "name": "cpu_rdy", + "name": "spi_controller/active", "width": 1, "probe_type": 1 } @@ -282,7 +192,7 @@ }, { "name": "la0_clk", - "net": "i_sysclk", + "net": "clk_50", "path": [] }, { @@ -422,868 +332,35 @@ }, { "name": "la0_probe5", - "net": "cpu_nmib", - "path": [] - }, - { - "name": "la0_probe6", - "net": "cpu_irqb", - "path": [] - }, - { - "name": "la0_probe7[0]", - "net": "cpu_data_out[0]", - "path": [] - }, - { - "name": "la0_probe7[1]", - "net": "cpu_data_out[1]", - "path": [] - }, - { - "name": "la0_probe7[2]", - "net": "cpu_data_out[2]", - "path": [] - }, - { - "name": "la0_probe7[3]", - "net": "cpu_data_out[3]", - "path": [] - }, - { - "name": "la0_probe7[4]", - "net": "cpu_data_out[4]", - "path": [] - }, - { - "name": "la0_probe7[5]", - "net": "cpu_data_out[5]", - "path": [] - }, - { - "name": "la0_probe7[6]", - "net": "cpu_data_out[6]", - "path": [] - }, - { - "name": "la0_probe7[7]", - "net": "cpu_data_out[7]", - "path": [] - }, - { - "name": "la0_probe8", "net": "cpu_phi2", "path": [] }, { - "name": "la0_probe9", - "net": "o_dbg_wr_ack", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe10[0]", - "net": "next_counter[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe10[1]", - "net": "next_counter[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[0]", - "net": "o_data[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[1]", - "net": "o_data[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[2]", - "net": "o_data[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[3]", - "net": "o_data[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[4]", - "net": "o_data[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[5]", - "net": "o_data[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[6]", - "net": "o_data[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe11[7]", - "net": "o_data[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe12[0]", - "net": "next_state[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe12[1]", - "net": "next_state[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[0]", - "net": "w_data_i[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[1]", - "net": "w_data_i[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[2]", - "net": "w_data_i[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[3]", - "net": "w_data_i[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[4]", - "net": "w_data_i[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[5]", - "net": "w_data_i[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[6]", - "net": "w_data_i[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[7]", - "net": "w_data_i[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[8]", - "net": "w_data_i[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[9]", - "net": "w_data_i[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[10]", - "net": "w_data_i[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[11]", - "net": "w_data_i[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[12]", - "net": "w_data_i[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[13]", - "net": "w_data_i[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[14]", - "net": "w_data_i[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[15]", - "net": "w_data_i[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[16]", - "net": "w_data_i[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[17]", - "net": "w_data_i[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[18]", - "net": "w_data_i[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[19]", - "net": "w_data_i[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[20]", - "net": "w_data_i[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[21]", - "net": "w_data_i[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[22]", - "net": "w_data_i[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[23]", - "net": "w_data_i[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[24]", - "net": "w_data_i[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[25]", - "net": "w_data_i[25]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[26]", - "net": "w_data_i[26]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[27]", - "net": "w_data_i[27]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[28]", - "net": "w_data_i[28]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[29]", - "net": "w_data_i[29]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[30]", - "net": "w_data_i[30]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe13[31]", - "net": "w_data_i[31]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe14", - "net": "i_rwb", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[0]", - "net": "w_addr[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[1]", - "net": "w_addr[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[2]", - "net": "w_addr[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[3]", - "net": "w_addr[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[4]", - "net": "w_addr[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[5]", - "net": "w_addr[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[6]", - "net": "w_addr[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[7]", - "net": "w_addr[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[8]", - "net": "w_addr[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[9]", - "net": "w_addr[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[10]", - "net": "w_addr[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[11]", - "net": "w_addr[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[12]", - "net": "w_addr[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[13]", - "net": "w_addr[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[14]", - "net": "w_addr[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[15]", - "net": "w_addr[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[16]", - "net": "w_addr[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[17]", - "net": "w_addr[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[18]", - "net": "w_addr[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[19]", - "net": "w_addr[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[20]", - "net": "w_addr[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[21]", - "net": "w_addr[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[22]", - "net": "w_addr[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe15[23]", - "net": "w_addr[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[0]", - "net": "w_data_o[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[1]", - "net": "w_data_o[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[2]", - "net": "w_data_o[2]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[3]", - "net": "w_data_o[3]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[4]", - "net": "w_data_o[4]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[5]", - "net": "w_data_o[5]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[6]", - "net": "w_data_o[6]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[7]", - "net": "w_data_o[7]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[8]", - "net": "w_data_o[8]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[9]", - "net": "w_data_o[9]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[10]", - "net": "w_data_o[10]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[11]", - "net": "w_data_o[11]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[12]", - "net": "w_data_o[12]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[13]", - "net": "w_data_o[13]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[14]", - "net": "w_data_o[14]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[15]", - "net": "w_data_o[15]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[16]", - "net": "w_data_o[16]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[17]", - "net": "w_data_o[17]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[18]", - "net": "w_data_o[18]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[19]", - "net": "w_data_o[19]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[20]", - "net": "w_data_o[20]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[21]", - "net": "w_data_o[21]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[22]", - "net": "w_data_o[22]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[23]", - "net": "w_data_o[23]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[24]", - "net": "w_data_o[24]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[25]", - "net": "w_data_o[25]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[26]", - "net": "w_data_o[26]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[27]", - "net": "w_data_o[27]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[28]", - "net": "w_data_o[28]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[29]", - "net": "w_data_o[29]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[30]", - "net": "w_data_o[30]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe16[31]", - "net": "w_data_o[31]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe17", - "net": "i_cs", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[0]", - "net": "counter[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe18[1]", - "net": "counter[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[0]", - "net": "state[0]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe19[1]", - "net": "state[1]", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe20", - "net": "w_last", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe21", - "net": "w_data_valid", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe22", - "net": "w_wr_ack", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe23", - "net": "w_read", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe24", - "net": "w_write", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe25", - "net": "w_rd_ack", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe26", - "net": "w_rd_valid", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe27", - "net": "o_dbg_ref_req", - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "la0_probe28", - "net": "cpu_rdy", + "name": "la0_probe6", + "net": "spi_clk", "path": [] + }, + { + "name": "la0_probe7", + "net": "spi_mosi", + "path": [] + }, + { + "name": "la0_probe8", + "net": "sd_cs", + "path": [] + }, + { + "name": "la0_probe9", + "net": "spi_miso", + "path": [] + }, + { + "name": "la0_probe10", + "net": "active", + "path": [ + "spi_controller" + ] } ] } @@ -1297,13 +374,13 @@ ], "session": { "wizard": { - "data_depth": 4096, + "data_depth": 16384, "capture_control": false, "selected_nets": [ { "name": "cpu_data_in", "width": 8, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [], @@ -1313,7 +390,7 @@ { "name": "cpu_rwb", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] @@ -1321,7 +398,7 @@ { "name": "cpu_sync", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] @@ -1329,7 +406,7 @@ { "name": "cpu_resb", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] @@ -1337,260 +414,62 @@ { "name": "cpu_addr", "width": 16, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [], "net_idx_left": 15, "net_idx_right": 0 }, - { - "name": "cpu_nmib", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [] - }, - { - "name": "cpu_irqb", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [] - }, - { - "name": "cpu_data_out", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [], - "net_idx_left": 7, - "net_idx_right": 0 - }, { "name": "cpu_phi2", "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] }, { - "name": "o_dbg_wr_ack", + "name": "spi_clk", "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "next_counter", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "o_data", - "width": 8, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 7, - "net_idx_right": 0 - }, - { - "name": "next_state", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "w_data_i", - "width": 32, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 31, - "net_idx_right": 0 - }, - { - "name": "i_rwb", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_addr", - "width": 24, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 23, - "net_idx_right": 0 - }, - { - "name": "w_data_o", - "width": 32, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 31, - "net_idx_right": 0 - }, - { - "name": "i_cs", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "counter", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "state", - "width": 2, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ], - "net_idx_left": 1, - "net_idx_right": 0 - }, - { - "name": "w_last", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_data_valid", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_wr_ack", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_read", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_write", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_rd_ack", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "w_rd_valid", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "o_dbg_ref_req", - "width": 1, - "clk_domain": "i_sysclk", - "selected_probe_type": "DATA AND TRIGGER", - "child": [], - "path": [ - "u_sdram_adapter" - ] - }, - { - "name": "cpu_rdy", - "width": 1, - "clk_domain": "i_sysclk", + "clk_domain": "clk_50", "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] + }, + { + "name": "spi_mosi", + "width": 1, + "clk_domain": "clk_50", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [] + }, + { + "name": "sd_cs", + "width": 1, + "clk_domain": "clk_50", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [] + }, + { + "name": "spi_miso", + "width": 1, + "clk_domain": "clk_50", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [] + }, + { + "name": "active", + "width": 1, + "clk_domain": "clk_50", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [ + "spi_controller" + ] } ], "top_module": "super6502", diff --git a/hw/efinix_fpga/init_hex.mem b/hw/efinix_fpga/init_hex.mem index 15cd4f0..ad3eb76 100644 --- a/hw/efinix_fpga/init_hex.mem +++ b/hw/efinix_fpga/init_hex.mem @@ -1,207 +1,147 @@ @00000000 -4C 00 00 8D 11 02 8E 12 02 8D 18 02 8E 19 02 88 -B9 FF FF 8D 22 02 88 B9 FF FF 8D 21 02 8C 24 02 -20 FF FF A0 FF D0 E8 60 00 00 02 FB 00 00 00 00 -A2 FF 9A D8 A9 F0 85 00 A9 7E 85 01 20 7A FB 20 -05 F8 20 50 F0 58 20 29 F1 6C FC FF 20 F9 F7 00 -A0 00 F0 07 A9 50 A2 F0 4C 03 02 60 AD FF EF A2 -00 60 8D FF EF 60 20 0F F1 C9 0A D0 05 A9 0D 20 -0F F1 60 DA 5A A8 B2 00 AA A9 1B 20 0F F1 A9 5B -20 0F F1 98 20 0F F1 A9 3B 20 0F F1 8A 20 0F F1 -A9 48 20 0F F1 7A FA 60 DA A9 1B 20 0F F1 A9 63 -20 0F F1 68 60 40 DA BA 48 E8 E8 BD 00 01 29 10 -D0 06 68 FA 20 28 F1 40 4C B8 F0 48 20 6B F9 8D -D8 EF 8E D9 EF A5 02 8D DA EF A5 03 8D DB EF 68 -8D DC EF 60 5A 85 08 86 09 AD DC EF 29 01 F0 F9 -AD D8 EF A0 00 91 08 AD D9 EF C8 91 08 AD DA EF -C8 91 08 AD DB EF C8 91 08 7A 60 AD DD EF A2 00 -60 48 AD DC EF 29 02 F0 F9 68 60 8D E6 EF 60 48 -8D E6 EF AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2 -00 60 AD E7 EF A2 00 60 60 20 9D F8 20 98 F0 A9 -C4 A2 FB 20 66 F8 A9 9D A2 FB 20 79 FA A0 02 20 -32 F8 20 AA F1 A9 D6 A2 FB 20 79 FA A0 02 20 32 -F8 20 F7 F2 A0 00 20 A7 FA A9 E6 A2 FB 20 79 FA -A0 03 20 21 F9 20 79 FA A0 04 20 32 F8 A0 01 20 -21 F9 20 36 F3 A9 EF A2 FB 20 79 FA A0 02 20 32 -F8 4C 87 F1 4C 81 F1 4C 84 F1 A9 B2 A2 FB 20 79 -FA AD FC FF AE FD FF 20 79 FA A0 04 20 32 F8 A2 -00 A9 00 4C A6 F1 20 CC F8 60 20 B7 F8 A9 1B A2 -FC 20 66 F8 A2 00 86 02 86 03 A9 00 20 89 F9 A2 -00 A9 00 20 BB F0 A9 0F A2 FC 20 79 FA A0 02 20 -32 F8 A2 01 A9 00 85 02 A9 00 85 03 A9 AA 20 89 -F9 A2 00 A9 08 20 BB F0 A9 02 20 3B F9 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00 B1 00 +C9 FF 20 FB F7 D0 03 4C 18 F2 A9 C1 A2 F8 20 27 +F7 A2 00 A9 01 4C B3 F2 20 E5 F5 A0 01 91 00 A0 +01 A2 00 B1 00 C9 02 20 14 F8 D0 03 4C 36 F2 20 +3F F6 A0 01 91 00 A2 00 A9 00 A0 06 20 69 F8 A0 +07 20 C1 F7 E0 03 D0 02 C9 E8 20 14 F8 F0 03 4C +55 F2 4C 61 F2 A0 06 A2 00 A9 01 20 C7 F6 4C 3F +F2 A0 00 A2 00 18 A9 01 71 00 91 00 A0 01 A2 00 +B1 00 C9 00 20 F5 F7 D0 81 A2 00 A9 00 A0 06 20 +69 F8 A0 07 20 C1 F7 E0 03 D0 02 C9 E8 20 14 F8 +F0 03 4C 98 F2 4C A4 F2 A0 06 A2 00 A9 01 20 C7 +F6 4C 82 F2 A9 01 20 C8 F7 20 6B F5 A2 00 A9 00 +4C B3 F2 20 B1 F7 60 20 56 F7 A2 00 A9 00 20 D3 +F0 A2 00 A9 00 A0 01 20 69 F8 A0 02 20 C1 F7 E0 +03 D0 02 C9 E8 20 14 F8 F0 03 4C E0 F2 4C EC F2 +A0 01 A2 00 A9 01 20 C7 F6 4C CA F2 A2 00 A9 FF +20 D9 F0 A2 00 A9 00 20 D3 F0 A2 00 A9 00 A0 00 +91 00 A0 00 A2 00 B1 00 C9 50 20 14 F8 F0 03 4C +15 F3 4C 2A F3 A2 00 A9 FF 20 D9 F0 A0 00 A2 00 +18 A9 01 71 00 91 00 4C 02 F3 20 A7 F7 60 A9 00 +20 25 F8 20 40 F7 4C 59 F3 A0 01 A2 00 18 A9 01 +71 00 91 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D0 F0 E6 10 D0 EF 60 85 08 86 +09 20 68 F0 4C 2B F7 85 08 86 09 A0 00 B1 08 F0 +0E C8 84 10 20 5B F0 A4 10 D0 F2 E6 09 D0 EE 60 +A4 00 D0 02 C6 01 C6 00 60 A5 00 38 E9 02 85 00 +90 01 60 C6 01 60 A5 00 38 E9 03 85 00 90 01 60 +C6 01 60 A5 00 38 E9 04 85 00 90 01 60 C6 01 60 +A5 00 38 E9 06 85 00 90 01 60 C6 01 60 A5 00 38 +E9 07 85 00 90 01 60 C6 01 60 E6 00 D0 02 E6 01 +60 A0 01 B1 00 AA 88 B1 00 E6 00 F0 05 E6 00 F0 +03 60 E6 00 E6 01 60 A0 03 4C D7 F6 A0 05 4C D7 +F6 A0 08 4C D7 F6 85 08 86 09 A2 00 B1 08 60 A0 +01 B1 00 AA 88 B1 00 60 A2 00 18 65 00 48 8A 65 +01 AA 68 60 A9 00 AA A0 00 84 02 84 03 48 20 63 +F7 A0 03 A5 03 91 00 88 A5 02 91 00 88 8A 91 00 +68 88 91 00 60 D0 06 A2 00 8A 60 D0 FA A2 00 A9 +01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10 EF A2 00 +8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2 00 8A 2A +60 A0 00 B1 00 A4 00 F0 07 C6 00 A0 00 91 00 60 +C6 01 C6 00 91 00 60 A9 00 A2 00 48 A5 00 38 E9 +02 85 00 B0 02 C6 01 A0 01 8A 91 00 68 88 91 00 +60 48 84 10 A0 01 B1 00 85 09 88 B1 00 85 08 A4 +10 68 91 08 4C 99 F7 A0 00 91 00 C8 48 8A 91 00 +68 60 A9 25 85 08 A9 02 85 09 A9 00 A8 A2 02 F0 +0A 91 08 C8 D0 FB E6 09 CA D0 F6 C0 00 F0 05 91 +08 C8 D0 F7 60 45 72 72 6F 72 20 69 6E 69 74 20 +53 44 20 43 41 52 44 0D 0A 00 53 44 20 43 61 72 +64 20 69 6E 69 74 0D 0A 00 53 74 61 72 74 0D 0A +00 6F 70 5F 63 6F 6E 64 20 65 72 72 6F 72 0D 0A +00 49 46 20 43 6F 6E 64 0D 0A 00 47 6F 20 49 44 +4C 45 0D 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -254,4 +194,64 @@ CA D0 F6 C0 2C F0 05 91 08 C8 D0 F7 60 41 6E 64 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 A5 F0 30 F0 A6 F0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 9A F0 25 F0 9B F0 diff --git a/hw/efinix_fpga/ip/uart/ipm/component.pickle b/hw/efinix_fpga/ip/uart/ipm/component.pickle index 812cad0..2a652e3 100644 Binary files a/hw/efinix_fpga/ip/uart/ipm/component.pickle and b/hw/efinix_fpga/ip/uart/ipm/component.pickle differ diff --git a/hw/efinix_fpga/ip/uart/ipm/graph.pickle b/hw/efinix_fpga/ip/uart/ipm/graph.pickle index 2213ce4..115948e 100644 Binary files a/hw/efinix_fpga/ip/uart/ipm/graph.pickle and b/hw/efinix_fpga/ip/uart/ipm/graph.pickle differ diff --git a/hw/efinix_fpga/ip/uart/settings.json b/hw/efinix_fpga/ip/uart/settings.json index 182d6fc..cee281a 100644 --- a/hw/efinix_fpga/ip/uart/settings.json +++ b/hw/efinix_fpga/ip/uart/settings.json @@ -19,31 +19,16 @@ "ENABLE_PARITY": "1'b0", "FIX_BAUDRATE": "1'b1", "PARITY_MODE": "1'b0", - "BOOTUP_CHECK": "1'b1" + "BOOTUP_CHECK": "1'b0" }, "output": { "external_source_source": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh", "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v", "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd" - ], - "external_example_example": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/command_state.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/decoder.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/encoder.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/led_ctl.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/resets.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_defines.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo_top.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/user_register.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.peri.xml", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.xml", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_timing_T20.sdc", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_define.vh" + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh" ] }, "sw_version": "2023.1.150", - "generated_date": "2023-07-16T20:20:12.259229" + "generated_date": "2023-07-23T03:23:04.338270" } \ No newline at end of file diff --git a/hw/efinix_fpga/ip/uart/uart.v b/hw/efinix_fpga/ip/uart/uart.v index f80fc6d..3814be2 100644 --- a/hw/efinix_fpga/ip/uart/uart.v +++ b/hw/efinix_fpga/ip/uart/uart.v @@ -43,7 +43,7 @@ // //////////////////////////////////////////////////////////////////////////////// -`define IP_UUID _d1961caf8b8d4ca092806671a99095c2 +`define IP_UUID _8d7ceb45e0e64e208e634a02f6a59365 `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module uart ( @@ -69,7 +69,7 @@ input [7:0] tx_data .ENABLE_PARITY (1'b0), .FIX_BAUDRATE (1'b1), .PARITY_MODE (1'b0), -.BOOTUP_CHECK (1'b1) +.BOOTUP_CHECK (1'b0) ) u_top_uart( .tx_o ( tx_o ), .rx_i ( rx_i ), diff --git a/hw/efinix_fpga/ip/uart/uart_define.vh b/hw/efinix_fpga/ip/uart/uart_define.vh index 40752e0..a1de19d 100644 --- a/hw/efinix_fpga/ip/uart/uart_define.vh +++ b/hw/efinix_fpga/ip/uart/uart_define.vh @@ -49,4 +49,4 @@ localparam BAUD = 115200; localparam ENABLE_PARITY = 1'b0; localparam FIX_BAUDRATE = 1'b1; localparam PARITY_MODE = 1'b0; -localparam BOOTUP_CHECK = 1'b1; +localparam BOOTUP_CHECK = 1'b0; diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile index 2befbaf..c3b0f2e 100644 --- a/hw/efinix_fpga/simulation/Makefile +++ b/hw/efinix_fpga/simulation/Makefile @@ -1,4 +1,4 @@ -TARGETS= timer interrupt_controller +TARGETS= timer interrupt_controller spi_controller TB=$(patsubst %, %_tb.sv, $(TARGETS)) all: $(TARGETS) @@ -6,6 +6,9 @@ all: $(TARGETS) timer: timer_tb.sv iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv +spi_controller: spi_controller_tb.sv ../spi_controller.sv + iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv + interrupt_controller: interrupt_controller_tb.sv iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv diff --git a/hw/efinix_fpga/simulation/spi_controller_tb.sv b/hw/efinix_fpga/simulation/spi_controller_tb.sv new file mode 100644 index 0000000..ad20da4 --- /dev/null +++ b/hw/efinix_fpga/simulation/spi_controller_tb.sv @@ -0,0 +1,102 @@ +module sim(); + +timeunit 10ns; +timeprecision 1ns; + +logic clk_50; + +logic i_clk; +logic i_rst; + +logic i_cs; +logic i_rwb; +logic [1:0] i_addr; +logic [7:0] i_data; +logic [7:0] o_data; + +logic o_spi_cs; +logic o_spi_clk; +logic o_spi_mosi; +logic i_spi_miso; + +spi_controller dut(.*); + +always #1 clk_50 = clk_50 === 1'b0; +always #100 i_clk = i_clk === 1'b0; + +task write_reg(input logic [2:0] _addr, input logic [7:0] _data); + @(negedge i_clk); + i_cs <= '1; + i_addr <= _addr; + i_rwb <= '0; + i_data <= '1; + @(posedge i_clk); + i_data <= _data; + @(negedge i_clk); + i_cs <= '0; + i_rwb <= '1; +endtask + +task read_reg(input logic [2:0] _addr, output logic [7:0] _data); + @(negedge i_clk); + i_cs <= '1; + i_addr <= _addr; + i_rwb <= '1; + i_data <= '1; + @(posedge i_clk); + _data <= o_data; + @(negedge i_clk); + i_cs <= '0; + i_rwb <= '1; +endtask + +initial +begin + $dumpfile("spi_controller.vcd"); + $dumpvars(0,sim); +end + +logic [7:0] data; + +initial begin + i_rst <= '1; + repeat(5) @(posedge i_clk); + i_cs <= '0; + i_rwb <= '1; + i_addr <= '0; + i_rst <= '0; + + repeat(5) @(posedge i_clk); + + write_reg(3, 1); + write_reg(2, 8'hFF); + data = (1 << 7); + while(data & (1 << 7)) begin + read_reg(3, data); + end + write_reg(3, 0); + read_reg(1, data); + assert(data == 8'h55); + + repeat(50) @(posedge i_clk); + + $finish(); +end + + +logic [7:0] _spi_device_data; + +initial begin + _spi_device_data <= 8'h55; +end + +always @(edge o_spi_clk) begin + if (o_spi_cs == '0) begin + if (o_spi_clk == '1) + i_spi_miso <= _spi_device_data[7]; + if (o_spi_clk == '0) + _spi_device_data <= _spi_device_data << 1; + end +end + +endmodule diff --git a/hw/efinix_fpga/spi_controller.sv b/hw/efinix_fpga/spi_controller.sv new file mode 100644 index 0000000..2d085e4 --- /dev/null +++ b/hw/efinix_fpga/spi_controller.sv @@ -0,0 +1,97 @@ +module spi_controller( + input i_clk, + input i_rst, + + input i_cs, + input i_rwb, + input [1:0] i_addr, + input [7:0] i_data, + output logic [7:0] o_data, + + output o_spi_cs, + output o_spi_clk, + output o_spi_mosi, + input i_spi_miso +); + + +// We need a speed register +// an input data register +// and an output data register +// and then a control register for cs + +logic [7:0] r_baud_rate; +logic [7:0] r_input_data; +logic [7:0] r_output_data; +logic [7:0] r_control; + +logic [8:0] r_clock_counter; + +logic active; +logic [2:0] count; +logic spi_clk; + +logic r_spi_mosi; + +assign o_spi_cs = ~r_control[0]; +assign o_spi_clk = spi_clk; +assign o_spi_mosi = r_spi_mosi; + +always @(negedge i_clk) begin + if (i_rst) begin + r_baud_rate <= 8'h1; + r_input_data <= '0; + r_output_data <= '0; + r_control <= '0; + r_clock_counter <= '0; + count <= '0; + spi_clk <= '0; + active <= '0; + end else begin + if (~i_rwb & i_cs) begin + unique case (i_addr) + 0: r_baud_rate <= i_data; + 1:; + 2: begin + r_output_data <= i_data; + active <= '1; + end + 3: r_control <= i_data; + endcase + end + + if (active) begin + r_spi_mosi <= r_output_data[7]; + r_clock_counter <= r_clock_counter + 9'b1; + if (r_clock_counter >= r_baud_rate) begin + r_clock_counter <= '0; + spi_clk <= ~spi_clk; + // rising edge + if (spi_clk == '0) begin + r_output_data <= r_output_data << 1; + count <= count + 1; + end + // falling edge + if (spi_clk == '1) begin + r_input_data <= {r_input_data[6:0], i_spi_miso}; + if (count == '0) begin + active <= '0; + end + end + end + + end + end +end + +always_comb begin + unique case (i_addr) + 0: o_data = r_baud_rate; + 1: o_data = r_input_data; + 2:; + 3: o_data = {active, r_control[6:0]}; + endcase +end + + +endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml index c44660e..d32a564 100644 --- a/hw/efinix_fpga/super6502.peri.xml +++ b/hw/efinix_fpga/super6502.peri.xml @@ -1,5 +1,5 @@ - + @@ -306,21 +306,17 @@ - - - - - - - - - - - - + + + + + + + + diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index c0d8457..abe90d8 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -41,30 +41,12 @@ module super6502 output uart_tx, output sd_cs, - output sd_clk, - - input sd_cmd_IN, - output sd_cmd_OUT, - output sd_cmd_OE, - - input sd_data_IN, - output sd_data_OUT, - output sd_data_OE + output spi_clk, + output spi_mosi, + + input spi_miso ); -assign sd_cs = '1; - -logic o_sd_cmd, i_sd_cmd; -logic o_sd_data, i_sd_data; - -assign i_sd_cmd = sd_cmd_IN; -assign sd_cmd_OUT = '0; -assign sd_cmd_OE = ~o_sd_cmd; - -assign i_sd_data = sd_data_IN; -assign sd_data_OUT = '0; -assign sd_data_OE = ~o_sd_data; - assign pll_cpu_reset = '1; assign o_pll_reset = '1; @@ -97,7 +79,7 @@ logic w_timer_cs; logic w_multiplier_cs; logic w_divider_cs; logic w_uart_cs; -logic w_sdcard_cs; +logic w_spi_cs; addr_decode u_addr_decode( .i_addr(cpu_addr), @@ -107,7 +89,7 @@ addr_decode u_addr_decode( .o_multiplier_cs(w_multiplier_cs), .o_divider_cs(w_divider_cs), .o_uart_cs(w_uart_cs), - .o_sdcard_cs(w_sdcard_cs), + .o_spi_cs(w_spi_cs), .o_sdram_cs(w_sdram_cs) ); @@ -117,7 +99,7 @@ logic [7:0] w_timer_data_out; logic [7:0] w_multiplier_data_out; logic [7:0] w_divider_data_out; logic [7:0] w_uart_data_out; -logic [7:0] w_sdcard_data_out; +logic [7:0] w_spi_data_out; logic [7:0] w_sdram_data_out; always_comb begin @@ -133,8 +115,8 @@ always_comb begin cpu_data_out = w_divider_data_out; else if (w_uart_cs) cpu_data_out = w_uart_data_out; - else if (w_sdcard_cs) - cpu_data_out = w_sdcard_data_out; + else if (w_spi_cs) + cpu_data_out = w_spi_data_out; else if (w_sdram_cs) cpu_data_out = w_sdram_data_out; else @@ -206,28 +188,19 @@ uart_wrapper u_uart( .irqb(w_uart_irqb) ); -logic sd_clk; -always @(posedge clk_2) begin - sd_clk <= ~sd_clk; -end +spi_controller spi_controller( + .i_clk(clk_2), + .i_rst(~cpu_resb), + .i_cs(w_spi_cs), + .i_rwb(cpu_rwb), + .i_addr(cpu_addr[1:0]), + .i_data(cpu_data_in), + .o_data(w_spi_data_out), - -sd_controller sd_controller( - .clk(clk_2), - .sd_clk(sd_clk), - .rst(rst), - .addr(cpu_addr[2:0]), - .data(cpu_data_in), - .cs(w_sdcard_cs), - .rw(cpu_rwb), - - .i_sd_cmd(i_sd_cmd), - .o_sd_cmd(o_sd_cmd), - - .i_sd_data(i_sd_data), - .o_sd_data(o_sd_data), - - .data_out(w_sdcard_data_out) + .o_spi_cs(sd_cs), + .o_spi_clk(spi_clk), + .o_spi_mosi(spi_mosi), + .i_spi_miso(spi_miso) ); diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 3843189..495eacf 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + @@ -19,6 +19,7 @@ + @@ -62,11 +63,11 @@ + + - - diff --git a/sw/bootloader/devices/io.inc65 b/sw/bootloader/devices/io.inc65 index 9e797f5..42b0910 100644 --- a/sw/bootloader/devices/io.inc65 +++ b/sw/bootloader/devices/io.inc65 @@ -6,7 +6,8 @@ UART_STATUS = UART + 1 LED = $efff SW = LED -SD_ARG = $efd8 -SD_CMD = $efdc -SD_DATA = $efdd - +SPI_BAUD = $efd8 +SPI_INPUT = $efd9 +SPI_OUTPUT = $efda +SPI_CTRL = $efdb +SPI_STATUS = SPI_CTRL \ No newline at end of file diff --git a/sw/bootloader/devices/sd_card.c b/sw/bootloader/devices/sd_card.c index 4e548ba..22d4f54 100644 --- a/sw/bootloader/devices/sd_card.c +++ b/sw/bootloader/devices/sd_card.c @@ -1,89 +1,437 @@ -#include #include -#include "devices/sd_card.h" +#include "sd_card.h" +#include "sd_print.h" +#include "spi.h" -void sd_init() { - uint32_t resp; - uint8_t attempts, i; +/******************************************************************************* + Initialize SD card +*******************************************************************************/ +uint8_t SD_init() +{ + uint16_t i; - cputs("In sd_init\n"); + uint8_t res[5], cmdAttempts = 0; - sd_card_command(0, 0); + SD_powerUpSeq(); - cprintf("Sent Reset\n"); + while((res[0] = SD_goIdleState()) != SD_IN_IDLE_STATE) + { + cmdAttempts++; + if(cmdAttempts == CMD0_MAX_ATTEMPTS) + { + cputs("Go IDLE\r\n"); + return SD_ERROR; + } + } - sd_card_command(0x000001aa, 8); - sd_card_resp(&resp); - cprintf("CMD8: %lx\n", resp); + for (i = 0; i < 1000; i++); - attempts = 0; - do { - if (attempts > 100) { - cprintf("SD Timed out"); - return; - } - sd_card_command(0, 55); - sd_card_resp(&resp); - sd_card_command(0x40180000, 41); - sd_card_resp(&resp); - cprintf("CMD41: %lx\n", resp); + SD_sendIfCond(res); + if(res[0] != SD_IN_IDLE_STATE) + { + cputs("IF Cond\r\n"); + return SD_ERROR; + } - //10ms loop? - for (i = 0; i < 255; i++); + if(res[4] != 0xAA) + { + return SD_ERROR; + } - attempts++; - } while (resp != 0); + cmdAttempts = 0; + do + { + if(cmdAttempts == CMD55_MAX_ATTEMPTS) + { + cputs("op_cond error\r\n"); + return SD_ERROR; + } - sd_card_command(0, 2); - sd_card_resp(&resp); - cprintf("CMD2: %lx\n", resp); + res[0] = SD_sendApp(); + if(SD_R1_NO_ERROR(res[0])) + { + res[0] = SD_sendOpCond(); + } + + for (i = 0; i < 1000; i++); + + cmdAttempts++; + } + while(res[0] != SD_READY); + + for (i = 0; i < 1000; i++); + + SD_readOCR(res); + + return SD_SUCCESS; } -uint16_t sd_get_rca() { - uint32_t resp; +/* +// Send a command with starting end ending clock pulses +uint8_t res1_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + uint8_t res1; + // assert chip select + spi_exchange(0xFF); + spi_select(0); + spi_exchange(0xFF); - sd_card_command(0, 3); - resp = 0; - sd_card_resp(&resp); + // send CMD0 + SD_command(cmd, arg, crc); - //cprintf("CMD3: %lx\n", resp); + // read response + res1 = SD_readRes1(); - return resp >> 16; + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); + + return res1; +} +*/ + +/******************************************************************************* + Run power up sequence +*******************************************************************************/ +/* +void SD_powerUpSeq() +{ + uint16_t i; + uint8_t j; + + // make sure card is deselected + spi_deselect(0); + + // give SD card time to power up + for (i = 0; i < 1000; i++); + + + // select SD card + spi_exchange(0xFF); + spi_deselect(0); + + // send 80 clock cycles to synchronize + for(j = 0; j < SD_INIT_CYCLES; j++) + spi_exchange(0xFF); +} +*/ + +/******************************************************************************* + Send command to SD card +*******************************************************************************/ +/* +void SD_command(uint8_t cmd, uint32_t arg, uint8_t crc) +{ + // transmit command to sd card + spi_exchange(cmd|0x40); + + // transmit argument + spi_exchange((uint8_t)(arg >> 24)); + spi_exchange((uint8_t)(arg >> 16)); + spi_exchange((uint8_t)(arg >> 8)); + spi_exchange((uint8_t)(arg)); + + // transmit crc + spi_exchange(crc|0x01); +} +*/ + +/******************************************************************************* + Read R1 from SD card +*******************************************************************************/ +/* +uint8_t SD_readRes1() +{ + uint8_t i = 0, res1; + + // keep polling until actual data received + while((res1 = spi_exchange(0xFF)) == 0xFF) + { + i++; + + // if no data received for 8 bytes, break + if(i > 8) break; + } + + return res1; +} +*/ + +/******************************************************************************* + Read R2 from SD card +*******************************************************************************/ +/* +void SD_readRes2(uint8_t *res) +{ + // read response 1 in R2 + res[0] = SD_readRes1(); + + // read final byte of response + res[1] = spi_exchange(0xFF); +} +*/ + +/******************************************************************************* + Read R3 from SD card +*******************************************************************************/ +/* +void SD_readRes3(uint8_t *res) +{ + // read response 1 in R3 + res[0] = SD_readRes1(); + + // if error reading R1, return + if(res[0] > 1) return; + + // read remaining bytes + SD_readBytes(res + 1, R3_BYTES); +} +*/ + +/******************************************************************************* + Read R7 from SD card +*******************************************************************************/ +/* +void SD_readRes7(uint8_t *res) +{ + // read response 1 in R7 + res[0] = SD_readRes1(); + + // if error reading R1, return + if(res[0] > 1) return; + + // read remaining bytes + SD_readBytes(res + 1, R7_BYTES); +} +*/ + +/******************************************************************************* + Read specified number of bytes from SD card +*******************************************************************************/ +/* +void SD_readBytes(uint8_t *res, uint8_t n) +{ + while(n--) *res++ = spi_exchange(0xFF); +} +*/ + +/******************************************************************************* + Command Idle State (CMD0) +*******************************************************************************/ +uint8_t SD_goIdleState() +{ + return res1_cmd(CMD0, CMD0_ARG, CMD0_CRC); } -uint16_t sd_select_card(uint16_t rca) { - uint32_t resp; +/******************************************************************************* + Send Interface Conditions (CMD8) +*******************************************************************************/ +void SD_sendIfCond(uint8_t *res) +{ + // assert chip select + spi_exchange(0xFF); + spi_select(0); + spi_exchange(0xFF); - sd_card_command((uint32_t)rca << 16, 7); - sd_card_resp(&resp); + // send CMD8 + SD_command(CMD8, CMD8_ARG, CMD8_CRC); - return (uint16_t) resp; + // read response + SD_readRes7(res); + //SD_readBytes(res + 1, R7_BYTES); + + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); } -uint16_t sd_get_status(uint16_t rca) { - uint32_t resp; +/******************************************************************************* + Read Status +*******************************************************************************/ +void SD_sendStatus(uint8_t *res) +{ + // assert chip select + spi_exchange(0xFF); + spi_select(0); + spi_exchange(0xFF); - sd_card_command((uint32_t)rca << 16, 13); - sd_card_resp(&resp); + // send CMD13 + SD_command(CMD13, CMD13_ARG, CMD13_CRC); - return (uint16_t) resp; + // read response + SD_readRes2(res); + + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); } -void sd_readblock(uint32_t addr, void* buf) { - uint32_t resp; - int i; +/******************************************************************************* + Read single 512 byte block + token = 0xFE - Successful read + token = 0x0X - Data error + token = 0xFF - timeout +*******************************************************************************/ +uint8_t SD_readSingleBlock(uint32_t addr, uint8_t *buf, uint8_t *token) +{ + uint8_t res1, read; + uint16_t readAttempts; + uint16_t i; - sd_card_command(addr, 17); - sd_card_resp(&resp); - //cprintf("CMD17: %lx\n", resp); + // set token to none + *token = 0xFF; - sd_card_wait_for_data(); + // assert chip select + spi_exchange(0xFF); + spi_select(0); + spi_exchange(0xFF); - //cprintf("Read data: \n"); - for (i = 0; i < 512; i++){ - ((uint8_t*)buf)[i] = sd_card_read_byte(); - } + // send CMD17 + SD_command(CMD17, addr, CMD17_CRC); - //cprintf("\n"); + // read R1 + res1 = SD_readRes1(); + + // if response received from card + if(res1 != 0xFF) + { + // wait for a response token (timeout = 100ms) + readAttempts = 0; + while(++readAttempts != SD_MAX_READ_ATTEMPTS) + if((read = spi_exchange(0xFF)) != 0xFF) break; + + // if response token is 0xFE + if(read == SD_START_TOKEN) + { + // read 512 byte block + for(i = 0; i < SD_BLOCK_LEN; i++) *buf++ = spi_exchange(0xFF); + + // read 16-bit CRC + spi_exchange(0xFF); + spi_exchange(0xFF); + } + + // set token to card response + *token = read; + } + + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); + + return res1; +} + +#define SD_MAX_WRITE_ATTEMPTS 3907 + +/******************************************************************************* +Write single 512 byte block +token = 0x00 - busy timeout +token = 0x05 - data accepted +token = 0xFF - response timeout +*******************************************************************************/ +uint8_t SD_writeSingleBlock(uint32_t addr, uint8_t *buf, uint8_t *token) +{ + uint16_t readAttempts; + uint8_t res1, read; + uint16_t i; + + /* + + // set token to none + *token = 0xFF; + + // assert chip select + spi_exchange(0xFF); + spi_select(0); + spi_exchange(0xFF); + + // send CMD24 + SD_command(CMD24, addr, CMD24_CRC); + + // read response + res1 = SD_readRes1(); + + // if no error + if(res1 == SD_READY) + { + // send start token + spi_exchange(SD_START_TOKEN); + + // write buffer to card + for(i = 0; i < SD_BLOCK_LEN; i++) spi_exchange(buf[i]); + + // wait for a response (timeout = 250ms) + readAttempts = 0; + while(++readAttempts != SD_MAX_WRITE_ATTEMPTS) + if((read = spi_exchange(0xFF)) != 0xFF) { *token = 0xFF; break; } + + // if data accepted + if((read & 0x1F) == 0x05) + { + // set token to data accepted + *token = 0x05; + + // wait for write to finish (timeout = 250ms) + readAttempts = 0; + while(spi_exchange(0xFF) == 0x00) + if(++readAttempts == SD_MAX_WRITE_ATTEMPTS) { *token = 0x00; break; } + } + } + + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); + + */ + + return res1; +} + +/******************************************************************************* + Reads OCR from SD Card +*******************************************************************************/ +void SD_readOCR(uint8_t *res) +{ + uint8_t tmp; + + // assert chip select + spi_exchange(0xFF); + spi_select(0); + tmp = spi_exchange(0xFF); + + if(tmp != 0xFF) while(spi_exchange(0xFF) != 0xFF) ; + + // send CMD58 + SD_command(CMD58, CMD58_ARG, CMD58_CRC); + + // read response + SD_readRes3(res); + + // deassert chip select + spi_exchange(0xFF); + spi_deselect(0); + spi_exchange(0xFF); +} + +/******************************************************************************* + Send application command (CMD55) +*******************************************************************************/ +uint8_t SD_sendApp() +{ + return res1_cmd(CMD55, CMD55_ARG, CMD55_CRC);; +} + +/******************************************************************************* + Send operating condition (ACMD41) +*******************************************************************************/ +uint8_t SD_sendOpCond() +{ + return res1_cmd(ACMD41, ACMD41_ARG, ACMD41_CRC); } diff --git a/sw/bootloader/devices/sd_card.h b/sw/bootloader/devices/sd_card.h index 7e3cb00..3e9304d 100644 --- a/sw/bootloader/devices/sd_card.h +++ b/sw/bootloader/devices/sd_card.h @@ -3,16 +3,78 @@ #include -void sd_init(); -uint16_t sd_get_rca(); -uint16_t sd_select_card(uint16_t rca); -uint16_t sd_get_status(uint16_t rca); -void sd_readblock(uint32_t addr, void* buf); +// command definitions +#define CMD0 0 +#define CMD0_ARG 0x00000000 +#define CMD0_CRC 0x94 +#define CMD8 8 +#define CMD8_ARG 0x0000001AA +#define CMD8_CRC 0x86 +#define CMD9 9 +#define CMD9_ARG 0x00000000 +#define CMD9_CRC 0x00 +#define CMD10 9 +#define CMD10_ARG 0x00000000 +#define CMD10_CRC 0x00 +#define CMD13 13 +#define CMD13_ARG 0x00000000 +#define CMD13_CRC 0x00 +#define CMD17 17 +#define CMD17_CRC 0x00 +#define CMD24 24 +#define CMD24_CRC 0x00 +#define CMD55 55 +#define CMD55_ARG 0x00000000 +#define CMD55_CRC 0x00 +#define CMD58 58 +#define CMD58_ARG 0x00000000 +#define CMD58_CRC 0x00 +#define ACMD41 41 +#define ACMD41_ARG 0x40000000 +#define ACMD41_CRC 0x00 -void sd_card_command(uint32_t arg, uint8_t cmd); +#define SD_IN_IDLE_STATE 0x01 +#define SD_READY 0x00 +#define SD_R1_NO_ERROR(X) X < 0x02 -void sd_card_resp(uint32_t* resp); -uint8_t sd_card_read_byte(); -void sd_card_wait_for_data(); +#define R3_BYTES 4 +#define R7_BYTES 4 -#endif +#define CMD0_MAX_ATTEMPTS 255 +#define CMD55_MAX_ATTEMPTS 255 +#define SD_ERROR 1 +#define SD_SUCCESS 0 +#define SD_MAX_READ_ATTEMPTS 1563 +#define SD_READ_START_TOKEN 0xFE +#define SD_INIT_CYCLES 80 + +#define SD_START_TOKEN 0xFE +#define SD_ERROR_TOKEN 0x00 + +#define SD_DATA_ACCEPTED 0x05 +#define SD_DATA_REJECTED_CRC 0x0B +#define SD_DATA_REJECTED_WRITE 0x0D + +#define SD_BLOCK_LEN 512 + +// SD functions +uint8_t SD_init(); +void SD_powerUpSeq(); +void SD_command(uint8_t cmd, uint32_t arg, uint8_t crc); +uint8_t SD_readRes1(); +void SD_readRes2(uint8_t *res); +void SD_readRes3(uint8_t *res); +void SD_readRes7(uint8_t *res); +void SD_readBytes(uint8_t *res, uint8_t n); +uint8_t SD_goIdleState(); +void SD_sendIfCond(uint8_t *res); +void SD_sendStatus(uint8_t *res); +void SD_readOCR(uint8_t *res); +uint8_t SD_sendApp(); +uint8_t SD_sendOpCond(); +uint8_t SD_readSingleBlock(uint32_t addr, uint8_t *buf, uint8_t *error); +uint8_t SD_writeSingleBlock(uint32_t addr, uint8_t *buf, uint8_t *res); + +uint8_t res1_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); + +#endif \ No newline at end of file diff --git a/sw/bootloader/devices/sd_card_asm.s b/sw/bootloader/devices/sd_card_asm.s index fe4f4e2..019286e 100644 --- a/sw/bootloader/devices/sd_card_asm.s +++ b/sw/bootloader/devices/sd_card_asm.s @@ -1,66 +1,190 @@ -.include "io.inc65" +.export _SD_command +.export _SD_readRes1 +.export _SD_readRes2 +.export _SD_readRes3 +.export _SD_readRes7 +.export _SD_readBytes +.export _SD_powerUpSeq +.export _res1_cmd -.importzp sp, sreg, ptr1 - -.export _sd_card_command -.export _sd_card_resp -.export _sd_card_read_byte -.export _sd_card_wait_for_data +.importzp sp, ptr1 .autoimport on -.code +.MACPACK generic -; Send sd card command. -; command is in A register, the args are on the stack -; I think the order is high byte first? -_sd_card_command: - pha +; void SD_command(uint8_t cmd, uint32_t arg, uint8_t crc) - jsr popeax - sta SD_ARG - stx SD_ARG+1 - lda sreg - sta SD_ARG+2 - lda sreg+1 - sta SD_ARG+3 +; The plan: push crc to stack, load arg into tmp1 through 4 - pla - sta SD_CMD - rts +.proc _SD_command: near -; void sd_card_resp(uint32_t* resp); -_sd_card_resp: - phy - sta ptr1 ; store pointer - stx ptr1+1 -@1: lda SD_CMD ; wait for status flag - and #$01 - beq @1 - lda SD_ARG - ldy #$0 - sta (ptr1),y - lda SD_ARG+1 - iny - sta (ptr1),y - lda SD_ARG+2 - iny - sta (ptr1),y - lda SD_ARG+3 - iny - sta (ptr1),y - ply + pha ; Push CRC to cpu stack + ldy #$04 + lda (sp),y ; Load CMD + ora #$40 ; start bit + jsr _spi_exchange + + dey +arg_loop: ; send ARG + lda (sp),y + jsr _spi_exchange + dey + bpl arg_loop + + pla ; Pull CRC from stack + ora #$01 ; stop bit + jsr _spi_exchange + jsr incsp5 ; pop all off stack rts -_sd_card_read_byte: - lda SD_DATA - ldx #$00 +.endproc + +; uint8_t SD_readRes1 (void) + +.proc _SD_readRes1: near +; Try to read/write up to 8 times, then return value + + ldx #$08 + +tryread: + lda #$ff + jsr _spi_exchange + cmp #$ff + bne end + dex + bne tryread + +end: ; x will be 0 here anyway rts -_sd_card_wait_for_data: - pha -@1: lda SD_CMD ; wait for status flag - and #$02 - beq @1 +.endproc + +; void SD_readRes2(uint8_t *res) + +.proc _SD_readRes2: near + + sta ptr1 ; store res in ptr1 + stx ptr1 + 1 + + jsr _SD_readRes1 ; get first response 1 + sta (ptr1) + + lda #$ff + jsr _spi_exchange ; get final byte of response + ldy #$01 + sta (ptr1),y + jsr incsp2 + rts + +.endproc + +; void SD_readBytes(uint8_t *res, uint8_t n) + +.proc _SD_readBytes: near + + tax + jsr popptr1 ; store res in ptr1 + +read: + lda #$ff ; read data first + jsr _spi_exchange + sta (ptr1) + inc ptr1 ; then increment res + bne @L1 + inc ptr1 + 1 +@L1: dex ; then decrement x + bne read ; and if x is zero we are done + rts + +.endproc + +; void SD_readRes7(uint8_t *res) + _SD_readRes7: +; void SD_readRes3(uint8_t *res) +.proc _SD_readRes3: near + + sta ptr1 ; store res in ptr1 + stx ptr1 + 1 + + jsr _SD_readRes1 ; read respopnse 1 in R3 + cmp #$02 ; if error reading R1, return + bge @L1 + + inc ptr1 ; read remaining bytes + bne @L2 + inc ptr1 +@L2: lda ptr1 ; push low byte + ldx ptr1 + 1 + jsr pushax + lda #$04 ; R3_BYTES + jsr _SD_readBytes + +@L1: rts + +.endproc + +; uint8_t res1_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) + +.proc _res1_cmd: near + + pha ; push crc to processor stack + lda #$ff + jsr _spi_exchange + lda #$00 ; this gets ignored anyway + jsr _spi_select + lda #$ff + jsr _spi_exchange + pla - rts \ No newline at end of file + jsr _SD_command ; rely on command to teardown stack + + jsr _SD_readRes1 + tay ; spi doesn't touch y + + lda #$ff + jsr _spi_exchange + lda #$00 ; this gets ignored anyway + jsr _spi_deselect + lda #$ff + jsr _spi_exchange + + tya + ldx #$00 ; Promote to integer + rts + +.endproc + +; void SD_powerUpSeq(void) + +.proc _SD_powerUpSeq: near + + lda #$00 + jsr _spi_deselect + jsr _sd_delay + lda #$ff + jsr _spi_exchange + lda #$00 + jsr _spi_deselect + + ldx #$50 ; SD_INIT_CYCLES +@L1: lda #$ff + jsr _spi_exchange + dex + bne @L1 + + rts + +.endproc + + +; 1ms delay approx. saves no registers +.proc _sd_delay: near + ldx #$01 ; delay loop: A*X*10 + 4 +@L1: lda #$c8 ; 1ms at 2MHz +@L2: dec ; 2 + bne @L2 ; 3 + dex ; 2 + bne @L1 ; 3 + rts +.endproc \ No newline at end of file diff --git a/sw/bootloader/devices/sd_print.c b/sw/bootloader/devices/sd_print.c new file mode 100644 index 0000000..2dcac25 --- /dev/null +++ b/sw/bootloader/devices/sd_print.c @@ -0,0 +1,188 @@ +#include + +#include "sd_print.h" +#include "sd_card.h" + +/* +void SD_printR1(uint8_t res) +{ + if(res == 0xFF) + { cputs("\tNo response\r\n"); return; } + if(res & 0x80) + { cputs("\tError: MSB = 1\r\n"); return; } + if(res == 0) + { cputs("\tCard Ready\r\n"); return; } + if(PARAM_ERROR(res)) + cputs("\tParameter Error\r\n"); + if(ADDR_ERROR(res)) + cputs("\tAddress Error\r\n"); + if(ERASE_SEQ_ERROR(res)) + cputs("\tErase Sequence Error\r\n"); + if(CRC_ERROR(res)) + cputs("\tCRC Error\r\n"); + if(ILLEGAL_CMD(res)) + cputs("\tIllegal Command\r\n"); + if(ERASE_RESET(res)) + cputs("\tErase Reset Error\r\n"); + if(IN_IDLE(res)) + cputs("\tIn Idle State\r\n"); +} +*/ + +/* +void SD_printR2(uint8_t *res) +{ + SD_printR1(res[0]); + + if(res[0] == 0xFF) return; + + if(res[1] == 0x00) + cputs("\tNo R2 Error\r\n"); + if(OUT_OF_RANGE(res[1])) + cputs("\tOut of Range\r\n"); + if(ERASE_PARAM(res[1])) + cputs("\tErase Parameter\r\n"); + if(WP_VIOLATION(res[1])) + cputs("\tWP Violation\r\n"); + if(CARD_ECC_FAILED(res[1])) + cputs("\tECC Failed\r\n"); + if(CC_ERROR(res[1])) + cputs("\tCC Error\r\n"); + if(ERROR(res[1])) + cputs("\tError\r\n"); + if(WP_ERASE_SKIP(res[1])) + cputs("\tWP Erase Skip\r\n"); + if(CARD_LOCKED(res[1])) + cputs("\tCard Locked\r\n"); +} +*/ + +/* +void SD_printR3(uint8_t *res) +{ + SD_printR1(res[0]); + + if(res[0] > 1) return; + + cputs("\tCard Power Up Status: "); + if(POWER_UP_STATUS(res[1])) + { + cputs("READY\r\n"); + cputs("\tCCS Status: "); + if(CCS_VAL(res[1])){ cputs("1\r\n"); } + else cputs("0\r\n"); + } + else + { + cputs("BUSY\r\n"); + } + + cputs("\tVDD Window: "); + if(VDD_2728(res[3])) cputs("2.7-2.8, "); + if(VDD_2829(res[2])) cputs("2.8-2.9, "); + if(VDD_2930(res[2])) cputs("2.9-3.0, "); + if(VDD_3031(res[2])) cputs("3.0-3.1, "); + if(VDD_3132(res[2])) cputs("3.1-3.2, "); + if(VDD_3233(res[2])) cputs("3.2-3.3, "); + if(VDD_3334(res[2])) cputs("3.3-3.4, "); + if(VDD_3435(res[2])) cputs("3.4-3.5, "); + if(VDD_3536(res[2])) cputs("3.5-3.6"); + cputs("\r\n"); +} +*/ + +/* +void SD_printR7(uint8_t *res) +{ + SD_printR1(res[0]); + + if(res[0] > 1) return; + + cputs("\tCommand Version: "); + cprintf("%x", CMD_VER(res[1])); + cputs("\r\n"); + + cputs("\tVoltage Accepted: "); + if(VOL_ACC(res[3]) == VOLTAGE_ACC_27_33) { + cputs("2.7-3.6V\r\n"); + } else if(VOL_ACC(res[3]) == VOLTAGE_ACC_LOW) { + cputs("LOW VOLTAGE\r\n"); + } else if(VOL_ACC(res[3]) == VOLTAGE_ACC_RES1) { + cputs("RESERVED\r\n"); + } else if(VOL_ACC(res[3]) == VOLTAGE_ACC_RES2) { + cputs("RESERVED\r\n"); + } else { + cputs("NOT DEFINED\r\n"); + } + + cputs("\tEcho: "); + cprintf("%x", res[4]); + cputs("\r\n"); +} +*/ + +/* +void SD_printCSD(uint8_t *buf) +{ + cputs("CSD:\r\n"); + + cputs("\tCSD Structure: "); + cprintf("%x", (buf[0] & 0b11000000) >> 6); + cputs("\r\n"); + + cputs("\tTAAC: "); + cprintf("%x", buf[1]); + cputs("\r\n"); + + cputs("\tNSAC: "); + cprintf("%x", buf[2]); + cputs("\r\n"); + + cputs("\tTRAN_SPEED: "); + cprintf("%x", buf[3]); + cputs("\r\n"); + + cputs("\tDevice Size: "); + cprintf("%x", buf[7] & 0b00111111); + cprintf("%x", buf[8]); + cprintf("%x", buf[9]); + cputs("\r\n"); +} +*/ + +void SD_printBuf(uint8_t *buf) +{ + uint8_t colCount = 0; + uint16_t i; + for(i = 0; i < SD_BLOCK_LEN; i++) + { + cprintf("%2x", *buf++); + if(colCount == 19) + { + cputs("\r\n"); + colCount = 0; + } + else + { + cputc(' '); + colCount++; + } + } + cputs("\r\n"); +} + +/* +void SD_printDataErrToken(uint8_t token) +{ + if(token & 0xF0) + cputs("\tNot Error token\r\n"); + if(SD_TOKEN_OOR(token)) + cputs("\tData out of range\r\n"); + if(SD_TOKEN_CECC(token)) + cputs("\tCard ECC failed\r\n"); + if(SD_TOKEN_CC(token)) + cputs("\tCC Error\r\n"); + if(SD_TOKEN_ERROR(token)) + cputs("\tError\r\n"); +} +*/ \ No newline at end of file diff --git a/sw/bootloader/devices/sd_print.h b/sw/bootloader/devices/sd_print.h new file mode 100644 index 0000000..fd42418 --- /dev/null +++ b/sw/bootloader/devices/sd_print.h @@ -0,0 +1,61 @@ +#ifndef SD_PRINT_H +#define SD_PRINT_H + + +#include + + +/* R1 MACROS */ +#define PARAM_ERROR(X) X & 0b01000000 +#define ADDR_ERROR(X) X & 0b00100000 +#define ERASE_SEQ_ERROR(X) X & 0b00010000 +#define CRC_ERROR(X) X & 0b00001000 +#define ILLEGAL_CMD(X) X & 0b00000100 +#define ERASE_RESET(X) X & 0b00000010 +#define IN_IDLE(X) X & 0b00000001 + +/* R2 MACROS */ +#define OUT_OF_RANGE(X) X & 0b10000000 +#define ERASE_PARAM(X) X & 0b01000000 +#define WP_VIOLATION(X) X & 0b00100000 +#define CARD_ECC_FAILED(X) X & 0b00010000 +#define CC_ERROR(X) X & 0b00001000 +#define ERROR(X) X & 0b00000100 +#define WP_ERASE_SKIP(X) X & 0b00000010 +#define CARD_LOCKED(X) X & 0b00000001 + +/* R3 MACROS */ +#define POWER_UP_STATUS(X) X & 0x40 +#define CCS_VAL(X) X & 0x40 +#define VDD_2728(X) X & 0b10000000 +#define VDD_2829(X) X & 0b00000001 +#define VDD_2930(X) X & 0b00000010 +#define VDD_3031(X) X & 0b00000100 +#define VDD_3132(X) X & 0b00001000 +#define VDD_3233(X) X & 0b00010000 +#define VDD_3334(X) X & 0b00100000 +#define VDD_3435(X) X & 0b01000000 +#define VDD_3536(X) X & 0b10000000 + +/* R7 MACROS */ +#define CMD_VER(X) ((X >> 4) & 0xF0) +#define VOL_ACC(X) (X & 0x1F) +#define VOLTAGE_ACC_27_33 0b00000001 +#define VOLTAGE_ACC_LOW 0b00000010 +#define VOLTAGE_ACC_RES1 0b00000100 +#define VOLTAGE_ACC_RES2 0b00001000 + +/* DATA ERROR TOKEN */ +#define SD_TOKEN_OOR(X) X & 0b00001000 +#define SD_TOKEN_CECC(X) X & 0b00000100 +#define SD_TOKEN_CC(X) X & 0b00000010 +#define SD_TOKEN_ERROR(X) X & 0b00000001 + +void SD_printR1(uint8_t res); +void SD_printR2(uint8_t *res); +void SD_printR3(uint8_t *res); +void SD_printR7(uint8_t *res); +void SD_printBuf(uint8_t *buf); +void SD_printDataErrToken(uint8_t token); + +#endif \ No newline at end of file diff --git a/sw/bootloader/devices/spi.h b/sw/bootloader/devices/spi.h new file mode 100644 index 0000000..61816d0 --- /dev/null +++ b/sw/bootloader/devices/spi.h @@ -0,0 +1,12 @@ +#ifndef _SPI_H +#define _SPI_H + +#include + +void spi_select(uint8_t id); +void spi_deselect(uint8_t id); +uint8_t spi_read(); +void spi_write(uint8_t data); +uint8_t spi_exchange(uint8_t data); + +#endif \ No newline at end of file diff --git a/sw/bootloader/devices/spi.s b/sw/bootloader/devices/spi.s new file mode 100644 index 0000000..5595a9a --- /dev/null +++ b/sw/bootloader/devices/spi.s @@ -0,0 +1,39 @@ +.include "io.inc65" + +.importzp zp, sreg + +.export _spi_select, _spi_deselect +.export _spi_read, _spi_write, _spi_exchange + +.autoimport on + +.code + +; void spi_select(uint8_t id) +; Select a (the) slave by pulling its CS line down +; TODO allow active high or active low CS +; TODO allow more than one slave +_spi_select: + lda #$1 ; Ignore whatever id is, 1 is the only option + sta SPI_CTRL + rts + +; void spi_deslect(uint8_t id) +; Deslect a slave by pulling its CS line up +; TODO allow active high or active low CS +_spi_deselect: + stz SPI_CTRL + rts + +; uint8_t spi_read() +_spi_read: + lda #$0 +; void spi_write(uint8_t data) +_spi_write: +; uint8_t spi_exchange(uint8_t data) +_spi_exchange: + sta SPI_OUTPUT +@1: lda SPI_CTRL + bmi @1 + lda SPI_INPUT + rts diff --git a/sw/bootloader/main.c b/sw/bootloader/main.c index 97290d3..d22de3d 100644 --- a/sw/bootloader/main.c +++ b/sw/bootloader/main.c @@ -6,6 +6,7 @@ #include "devices/board_io.h" #include "devices/uart.h" #include "devices/sd_card.h" +#include "devices/sd_print.h" #include "filesystem/fat.h" #define KERNEL_LOAD_ADDR 0xD000 @@ -13,40 +14,68 @@ uint8_t buf[512]; int main() { - uint16_t rca; - clrscr(); - cputs("Starting sd_init\n"); - cprintf("And testing cprintf\n"); + // array to hold responses + uint8_t res[5], token; + uint32_t addr = 0x00000000; + uint16_t i; - sd_init(); + cputs("Start\r\n"); - cprintf("finish sd_init\n"); + // initialize sd card + if(SD_init() != SD_SUCCESS) + { + cputs("Error\r\n"); + } + else + { + cputs("Success\r\n"); - rca = sd_get_rca(); - cprintf("rca: %x\n", rca); + // read sector 0 + cputs("\r\nReading sector: 0x"); + // ((uint8_t)(addr >> 24)); + // cprintf("%x", (uint8_t)(addr >> 16)); + // cprintf("%x", (uint8_t)(addr >> 8)); + // cprintf("%x", (uint8_t)addr); + res[0] = SD_readSingleBlock(addr, buf, &token); + cputs("\r\nResponse:\r\n"); + //SD_printR1(res[0]); - sd_select_card(rca); + // if no error, print buffer + if((res[0] == 0x00) && (token == SD_START_TOKEN)) + SD_printBuf(buf); + //else if error token received, print + else if(!(token & 0xF0)) + { + cputs("Error token:\r\n"); + //SD_printDataErrToken(token); + } - /* - fat_init(); + // update address to 0x00000100 + // addr = 0x00000100; - filename = (char*)malloc(FAT_MAX_FILE_NAME); + // // fill buffer with 0x55 + // for(i = 0; i < 512; i++) buf[i] = 0x55; - cluster = fat_parse_path_to_cluster("/kernel.bin"); - for (kernel_load = (uint8_t*)KERNEL_LOAD_ADDR; cluster < FAT_CLUSTERMASK; kernel_load+=(8*512)) { - cprintf("cluster: %lx\n", cluster); - cprintf("Writing to %p\n", kernel_load); - fat_read_cluster(cluster, kernel_load); - cluster = fat_get_chain_value(cluster); - } + // cputs("Writing 0x55 to sector: 0x"); + // cprintf("%x", (uint8_t)(addr >> 24)); + // cprintf("%x", (uint8_t)(addr >> 16)); + // cprintf("%x", (uint8_t)(addr >> 8)); + // cprintf("%x", (uint8_t)addr); - */ + // // write data to sector + // res[0] = SD_writeSingleBlock(addr, buf, &token); - cprintf("Done!\n"); + // cputs("\r\nResponse:\r\n"); + // //SD_printR1(res[0]); - for(;;); + // // if no errors writing + // if(res[0] == 0x00) + // { + // if(token == SD_DATA_ACCEPTED) + // cputs("Write successful\r\n"); + // } + } - cprintf("Reset vector: %x\n", *((uint16_t*)0xfffc)); + while(1) ; - return 0; }