Get block rom kind of working
This commit is contained in:
Byron Lathi
281
hw/efinix_fpga/ip/bram/bram_primitive.v
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281
hw/efinix_fpga/ip/bram/bram_primitive.v
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////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
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// / / \
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// / / .. / bram_primitive.v
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// / / .' /
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// __/ /.' / Description:
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 0.0 Initial rev
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//
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// *******************************
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module bram_primitive #(
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parameter FAMILY = 0, //0:Trion, 1:Titanium
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//Trion and Titanium parameters
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parameter WRITE_WIDTH = 16, // write width
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parameter WCLK_POLARITY = 1'b1, //wclk polarity, 0:falling edge, 1:rising edge
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parameter WCLKE_POLARITY = 1'b1, //wclke polarity, 0:active low, 1:active high
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parameter WE_POLARITY = 1'b1, //we polarity, 0:active low, 1:active high
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parameter WRITE_MODE = "READ_FIRST",//write mode, "READ_FIRST" :Old memory content is read. (default)
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// "WRITE_FIRST" :Write data is passed to the read port.
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// "READ_UNKNOWN": Read and writes are unsynchronized, therefore, the results of the address can conflict.
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parameter READ_WIDTH = 16, // read width
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parameter RCLK_POLARITY = 1'b1, // rclk polarity, 0:falling edge, 1:rising edge
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parameter RE_POLARITY = 1'b1, // re polarity, 0:active low , 1:active high
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parameter OUTPUT_REG = 1'b0, // Output register enable, 1:add pipe-line read register
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//Titanium extra paramters
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parameter RST_POLARITY = 1'b1, // rst polarity
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parameter RESET_RAM = "ASYNC", // reset mode on ram, "NONE": RST signals does not affect the RAM output.
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// "ASYNC": RAM output resets asynchronously to RCLK.
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// "SYNC": RAM output resets synchronously to RCLK.
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parameter RESET_OUTREG = "ASYNC", // reset mode on output register
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// "NONE": RST signals does not affect the RAM output register
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// "ASYNC": RAM output register resets asynchronously to RCLK.
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parameter WADDREN_POLARITY = 1'b1, // waddren polarity
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parameter RADDREN_POLARITY = 1'b1, // raddren polarity
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//Titanium Option for byte enable in WEN width = 2 when it is Mode 512x16 or 512x20
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parameter WEN_WIDTH = 1,
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parameter ini_index = 0
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)
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(
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//Trion and Titanium ports
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WCLK, // Write clock input
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WCLKE, // Write clock-enable input
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WE, // Write-enable input
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WADDR, // Write address input
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WDATA, // Write data input
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RCLK, // Read clock input
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RE, // Read-enable input
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RADDR, // Read address input
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RDATA, // Read data output
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//Titanium extra ports
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RST, // reset
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WADDREN, // write address enable
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RADDREN // read address enable
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);
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function integer address_map;
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input integer index;//Input data width parameter
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input integer type; //Mapped data width, Mapped Address Width for Ram 5K(Trion), Mapped Address Width for Ram 10K(Titanium), WEN width for Ram 5K(Trion), WEN width for Ram 10K(Titanium)
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case (index)
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0 : address_map= (type==0)? 1 :(type==1)? 12 :(type==2)? 13 :1;
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1 : address_map= (type==0)? 1 :(type==1)? 12 :(type==2)? 13 :1;
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2 : address_map= (type==0)? 2 :(type==1)? 11 :(type==2)? 12 :1;
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3 : address_map= (type==0)? 4 :(type==1)? 10 :(type==2)? 11 :1;
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4 : address_map= (type==0)? 4 :(type==1)? 10 :(type==2)? 11 :1;
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5 : address_map= (type==0)? 5 :(type==1)? 10 :(type==2)? 11 :1;
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6 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
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7 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
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8 : address_map= (type==0)? 8 :(type==1)? 9 :(type==2)? 10 :1;
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9 : address_map= (type==0)? 10 :(type==1)? 9 :(type==2)? 10 :1;
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10 : address_map= (type==0)? 10 :(type==1)? 9 :(type==2)? 10 :1;
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11 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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12 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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13 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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14 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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15 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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16 : address_map= (type==0)? 16 :(type==1)? 8 :(type==2)? 9 :1;
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17 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
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18 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
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19 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
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20 : address_map= (type==0)? 20 :(type==1)? 8 :(type==2)? 9 :1;
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endcase
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endfunction
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localparam WRITE_DATA_WIDTH = address_map(WRITE_WIDTH,0);
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localparam WRITE_ADDRESS_WIDTH = address_map(WRITE_WIDTH,(FAMILY==0)?1:2);
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localparam READ_DATA_WIDTH = address_map(READ_WIDTH,0);
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localparam READ_ADDRESS_WIDTH = address_map(READ_WIDTH,(FAMILY==0)?1:2);
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//Trion and Titanium ports
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input WCLK; // Write clock input
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input WCLKE; // Write clock-enable input
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input [WEN_WIDTH-1:0] WE; // Write-enable input
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input [WRITE_ADDRESS_WIDTH-1:0] WADDR; // Write address input
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input [WRITE_DATA_WIDTH-1:0] WDATA; // Write data input
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input RCLK; // Read clock input
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input RE; // Read-enable input
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input [READ_ADDRESS_WIDTH-1:0] RADDR; // Read address input
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output[READ_DATA_WIDTH-1:0]RDATA; // Read data output
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//Titanium extra ports
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input RST; // reset
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input WADDREN; // write address enable
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input RADDREN; // read address enable
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`include "bram_ini.vh"
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parameter filePath = "bram_ini.vh";
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integer fd;
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generate
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initial begin
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fd = $fopen(filePath, "r");
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$fclose(fd);
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end
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if (FAMILY==0)
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begin
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EFX_RAM_5K # (
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.WRITE_WIDTH (WRITE_WIDTH),
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.WCLK_POLARITY (WCLK_POLARITY),
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.WCLKE_POLARITY (WCLKE_POLARITY),
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.WE_POLARITY (WE_POLARITY),
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.WRITE_MODE (WRITE_MODE),
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.READ_WIDTH (READ_WIDTH),
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.RCLK_POLARITY (RCLK_POLARITY),
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.RE_POLARITY (RE_POLARITY),
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.OUTPUT_REG (OUTPUT_REG),
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.INIT_0 (bram_ini_table(ini_index,16'h0 )),
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.INIT_1 (bram_ini_table(ini_index,16'h1 )),
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.INIT_2 (bram_ini_table(ini_index,16'h2 )),
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.INIT_3 (bram_ini_table(ini_index,16'h3 )),
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.INIT_4 (bram_ini_table(ini_index,16'h4 )),
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.INIT_5 (bram_ini_table(ini_index,16'h5 )),
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.INIT_6 (bram_ini_table(ini_index,16'h6 )),
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.INIT_7 (bram_ini_table(ini_index,16'h7 )),
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.INIT_8 (bram_ini_table(ini_index,16'h8 )),
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.INIT_9 (bram_ini_table(ini_index,16'h9 )),
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.INIT_A (bram_ini_table(ini_index,16'hA )),
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.INIT_B (bram_ini_table(ini_index,16'hB )),
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.INIT_C (bram_ini_table(ini_index,16'hC )),
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.INIT_D (bram_ini_table(ini_index,16'hD )),
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.INIT_E (bram_ini_table(ini_index,16'hE )),
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.INIT_F (bram_ini_table(ini_index,16'hF )),
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.INIT_10 (bram_ini_table(ini_index,16'h10)),
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.INIT_11 (bram_ini_table(ini_index,16'h11)),
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.INIT_12 (bram_ini_table(ini_index,16'h12)),
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.INIT_13 (bram_ini_table(ini_index,16'h13))
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)
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ram5k (
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.WCLK(WCLK), // Write clock input
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.WE(WE[0]), // Write-enable input
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.WCLKE(WCLKE), // Write clock-enable input
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.WADDR(WADDR), // Write address input
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.WDATA(WDATA), // Write data input
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.RCLK(RCLK), // Read clock input
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.RE(RE), // Read-enable input
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.RADDR(RADDR), // Read address input
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.RDATA(RDATA) // Read data output
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);
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end
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else
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begin
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wire [1:0]w_wen_ram10;
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assign w_wen_ram10[0] = WE[0];
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if (WEN_WIDTH>1)
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assign w_wen_ram10[1] = WE[1];
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else if (WRITE_DATA_WIDTH >= 16 )
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assign w_wen_ram10[1] = WE[0];
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else
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assign w_wen_ram10[1] = 1'b0;
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EFX_RAM10 # (
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.WRITE_WIDTH (WRITE_WIDTH),
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.WCLK_POLARITY (WCLK_POLARITY),
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.WCLKE_POLARITY (WCLKE_POLARITY),
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.WE_POLARITY (WE_POLARITY),
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.WRITE_MODE (WRITE_MODE),
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.READ_WIDTH (READ_WIDTH),
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.RCLK_POLARITY (RCLK_POLARITY),
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.RE_POLARITY (RE_POLARITY),
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.OUTPUT_REG (OUTPUT_REG),
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//Titanium extra paramters
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.RST_POLARITY (RST_POLARITY), // rst polarity
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.RESET_RAM (RESET_RAM), // reset mode on ram
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.RESET_OUTREG (RESET_OUTREG), // reset mode on output register
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.WADDREN_POLARITY (WADDREN_POLARITY), // waddren polarity
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.RADDREN_POLARITY (RADDREN_POLARITY), // raddren polarity
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.INIT_0 (bram_ini_table(ini_index, 16'h0 )),
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.INIT_1 (bram_ini_table(ini_index, 16'h1 )),
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.INIT_2 (bram_ini_table(ini_index, 16'h2 )),
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.INIT_3 (bram_ini_table(ini_index, 16'h3 )),
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.INIT_4 (bram_ini_table(ini_index, 16'h4 )),
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.INIT_5 (bram_ini_table(ini_index, 16'h5 )),
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.INIT_6 (bram_ini_table(ini_index, 16'h6 )),
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.INIT_7 (bram_ini_table(ini_index, 16'h7 )),
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.INIT_8 (bram_ini_table(ini_index, 16'h8 )),
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.INIT_9 (bram_ini_table(ini_index, 16'h9 )),
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.INIT_A (bram_ini_table(ini_index, 16'hA )),
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.INIT_B (bram_ini_table(ini_index, 16'hB )),
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.INIT_C (bram_ini_table(ini_index, 16'hC )),
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.INIT_D (bram_ini_table(ini_index, 16'hD )),
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.INIT_E (bram_ini_table(ini_index, 16'hE )),
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.INIT_F (bram_ini_table(ini_index, 16'hF )),
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.INIT_10 (bram_ini_table(ini_index, 16'h10)),
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.INIT_11 (bram_ini_table(ini_index, 16'h11)),
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.INIT_12 (bram_ini_table(ini_index, 16'h12)),
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.INIT_13 (bram_ini_table(ini_index, 16'h13)),
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.INIT_14 (bram_ini_table(ini_index, 16'h14)),
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.INIT_15 (bram_ini_table(ini_index, 16'h15)),
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.INIT_16 (bram_ini_table(ini_index, 16'h16)),
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.INIT_17 (bram_ini_table(ini_index, 16'h17)),
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.INIT_18 (bram_ini_table(ini_index, 16'h18)),
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.INIT_19 (bram_ini_table(ini_index, 16'h19)),
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.INIT_1A (bram_ini_table(ini_index, 16'h1A)),
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.INIT_1B (bram_ini_table(ini_index, 16'h1B)),
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.INIT_1C (bram_ini_table(ini_index, 16'h1C)),
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.INIT_1D (bram_ini_table(ini_index, 16'h1D)),
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.INIT_1E (bram_ini_table(ini_index, 16'h1E)),
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.INIT_1F (bram_ini_table(ini_index, 16'h1F)),
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.INIT_20 (bram_ini_table(ini_index, 16'h20)),
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.INIT_21 (bram_ini_table(ini_index, 16'h21)),
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.INIT_22 (bram_ini_table(ini_index, 16'h22)),
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.INIT_23 (bram_ini_table(ini_index, 16'h23)),
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.INIT_24 (bram_ini_table(ini_index, 16'h24)),
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.INIT_25 (bram_ini_table(ini_index, 16'h25)),
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.INIT_26 (bram_ini_table(ini_index, 16'h26)),
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.INIT_27 (bram_ini_table(ini_index, 16'h27))
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)
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ram10k(
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.WCLK(WCLK), // Write clock input
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.WE(w_wen_ram10), // Write-enable input
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.WCLKE(WCLKE), // Write clock-enable input
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.WADDR(WADDR), // Write address input
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.WDATA(WDATA), // Write data input
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.RCLK(RCLK), // Read clock input
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.RE(RE), // Read-enable input
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.RADDR(RADDR), // Read address input
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.RDATA(RDATA), // Read data output
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//Titanium extra ports
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.RST (RST), // reset
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.WADDREN (WADDREN), // write address enable
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.RADDREN (RADDREN) // read address enable
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);
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end
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endgenerate
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endmodule
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