From 552fe8b6f86a8e1956e34a269d68fa7ef4006ad7 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Fri, 8 Apr 2022 12:25:17 -0500
Subject: [PATCH] Have valid crc when valid signal is present

Previously the crc would be reset after 1 clock cycle while the valid
signal was still high. Now the data is preserved in the valid state
until the load signal is asserted.
---
 hw/fpga/crc7.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/fpga/crc7.sv b/hw/fpga/crc7.sv
index 960f22c..e009826 100644
--- a/hw/fpga/crc7.sv
+++ b/hw/fpga/crc7.sv
@@ -95,6 +95,7 @@ always_comb begin
 
         VALID: begin
             valid =  ~load;
+            next_data = data;
             crc_out = data[6:0];
         end