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Update mm_testbench

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Byron Lathi
2022-04-07 10:48:10 -05:00
parent 7434621209
commit 5548f9d02a
2 changed files with 12 additions and 0 deletions
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5
hw/fpga/hvl/mm_testbench.sv
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@@ -6,6 +6,7 @@ timeprecision 1ns;
logic clk_50, clk, cs; logic clk_50, clk, cs;
logic rw, MM_cs; logic rw, MM_cs;
logic rst;
logic [3:0] RS, MA; logic [3:0] RS, MA;
logic [7:0] data_in; logic [7:0] data_in;
logic [7:0] data_out; logic [7:0] data_out;
@@ -56,6 +57,10 @@ task enable(logic [7:0] data);
endtask endtask
initial begin initial begin
rst <= '1;
repeat(5) @(posedge clk);
rst <= '0;
cpu_addr <= 16'h0abc; cpu_addr <= 16'h0abc;
write_reg(4'h0, 8'hcc); write_reg(4'h0, 8'hcc);
$display("Address: %x", mm_address); $display("Address: %x", mm_address);

7
hw/fpga/simulation/modelsim/mm_testbench.do
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@@ -15,3 +15,10 @@ add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
onfinish stop onfinish stop
run -all run -all
if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
echo Warning
quit -f -code 0
}
quit -code [coverage attribute -name TESTSTATUS -concise]