From 57efb41ae08cc9b18421ce3ec598442f8558c239 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 10 Oct 2023 21:39:10 -0700
Subject: [PATCH] Increase sim time, update verilog sd

---
 hw/efinix_fpga/simulation/src/sim_top.sv          | 2 +-
 hw/efinix_fpga/simulation/src/verilog-sd-emulator | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 2b22de3..4d18031 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -49,7 +49,7 @@ initial begin
     button_reset <= '0;
     repeat(10) @(r_clk_2);
     button_reset <= '1;
-    repeat(200000) @(r_clk_2);
+    repeat(1000000) @(r_clk_2);
     $finish();
 end
 
diff --git a/hw/efinix_fpga/simulation/src/verilog-sd-emulator b/hw/efinix_fpga/simulation/src/verilog-sd-emulator
index 3b3a8d7..9f0de55 160000
--- a/hw/efinix_fpga/simulation/src/verilog-sd-emulator
+++ b/hw/efinix_fpga/simulation/src/verilog-sd-emulator
@@ -1 +1 @@
-Subproject commit 3b3a8d7d1c774cfbd080c64ba78a72275431f2b3
+Subproject commit 9f0de55a0e992ec4187adedde8668a98a96bb7ae