Increase sim time, update verilog sd

2023-10-10 21:39:10 -07:00
parent 97622ac3bb
commit 57efb41ae0
2 changed files with 2 additions and 2 deletions
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -49,7 +49,7 @@ initial begin
    button_reset <= '0;
    repeat(10) @(r_clk_2);
    button_reset <= '1;
-    repeat(200000) @(r_clk_2);
+    repeat(1000000) @(r_clk_2);
    $finish();
 end
--- a/hw/efinix_fpga/simulation/src/verilog-sd-emulator
+++ b/hw/efinix_fpga/simulation/src/verilog-sd-emulator