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Refactor for FPGA synthesis

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This commit is contained in:
Byron Lathi
2023-10-19 18:57:42 -07:00
parent 03456607c9
commit 5a8d15de94
2 changed files with 97 additions and 86 deletions
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17
hw/efinix_fpga/src/mapper.sv
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@@ -10,6 +10,7 @@ module mapper(
);
logic [15:0] mm [16];
logic [15:0] mm_next [16];
logic [31:0] we;
@@ -27,6 +28,16 @@ always_comb begin
selected_mm = mm[i_cpu_addr[15:12]];
o_mapped_addr = {selected_mm[12:0], i_cpu_addr[11:0]};
for (int i = 0; i < 16; i++) begin
mm_next[i] = mm[i];
end
for (int i = 0; i < 32; i++) begin
if (we[i]) begin
mm_next[i/2][(i%2)*8 +: 8] = i_data;
end
end
end
always_ff @(negedge i_clk or posedge i_reset) begin
@@ -36,10 +47,8 @@ always_ff @(negedge i_clk or posedge i_reset) begin
end
end
for (int i = 0; i < 32; i++) begin
if (we[i]) begin
mm[i/2][(i%2)*8 +: 8] <= i_data;
end
for (int i = 0; i < 16; i++) begin
mm[i] <= mm_next[i];
end

4
hw/efinix_fpga/super6502.xml
View File

@@ -1,4 +1,5 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Sun Oct 15 2023 09:26:48 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Thu October 19 2023 18:55:10" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="sync" design_ood="" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -18,6 +19,7 @@
<efx:design_file name="src/crc7.sv" version="default" library="default"/>
<efx:design_file name="src/rom.sv" version="default" library="default"/>
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
<efx:design_file name="src/mapper.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>