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Get SD card working in SPI

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This commit is contained in:
Byron Lathi
2023-07-23 14:55:14 -07:00
parent 6a1a76db35
commit 5ca5fca29b
23 changed files with 1257 additions and 1931 deletions
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4
hw/efinix_fpga/addr_decode.sv
View File

@@ -8,7 +8,7 @@ module addr_decode
output o_multiplier_cs,
output o_divider_cs,
output o_uart_cs,
output o_sdcard_cs,
output o_spi_cs,
output o_sdram_cs
);
@@ -17,7 +17,7 @@ assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef;
assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7;
assign o_sdcard_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdf;
assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'h8000;

1189
hw/efinix_fpga/debug_profile.wizard.json
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File diff suppressed because it is too large Load Diff

406
hw/efinix_fpga/init_hex.mem
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@@ -1,207 +1,152 @@
@00000000
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65 6E 74 20 52 65 73 65 74 0A 00 49 6E 20 73 64
5F 69 6E 69 74 0A 00 43 4D 44 32 3A 20 25 6C 78
0A 00 43 4D 44 38 3A 20 25 6C 78 0A 00 30 31 32
33 34 35 36 37 38 39 41 42 43 44 45 46 2D 32 31
34 37 34 38 33 36 34 38 00 00 01 02 0C 09 0A 10
40 50 A0 D0 66 66 66 66 A6 88 88 66 66 66 66 66
66 66 66 66 09 00 00 00 00 00 00 00 33 33 33 33
33 00 00 00 50 55 55 25 22 22 22 22 22 22 22 22
22 02 00 00 40 44 44 14 11 11 11 11 11 11 11 11
11 01 00 70 00 00 00 00 00 00 00 00 00 00 00 00
18 98 65 00 85 00 90 02 E6 01 68 60 A0 00 F0 07
A9 45 A2 F0 4C 00 02 60 A9 00 85 08 A9 F0 85 09
A9 00 85 0A A9 02 85 0B A2 DA A9 FF 85 10 A0 00
E8 F0 0D B1 08 91 0A C8 D0 F6 E6 09 E6 0B D0 F0
E6 10 D0 EF 60 85 08 86 09 20 68 F0 4C 73 F7 85
08 86 09 A0 00 B1 08 F0 0E C8 84 10 20 5B F0 A4
10 D0 F2 E6 09 D0 EE 60 A4 00 D0 02 C6 01 C6 00
60 A5 00 38 E9 02 85 00 90 01 60 C6 01 60 A5 00
38 E9 03 85 00 90 01 60 C6 01 60 A5 00 38 E9 04
85 00 90 01 60 C6 01 60 A5 00 38 E9 06 85 00 90
01 60 C6 01 60 A5 00 38 E9 07 85 00 90 01 60 C6
01 60 E6 00 D0 02 E6 01 60 A0 01 B1 00 AA 88 B1
00 E6 00 F0 05 E6 00 F0 03 60 E6 00 E6 01 60 A0
03 4C 1F F7 A0 06 4C 1F F7 A0 08 4C 1F F7 85 08
86 09 A2 00 B1 08 60 A0 01 B1 00 AA 88 B1 00 60
A0 03 B1 00 85 03 88 B1 00 85 02 88 B1 00 AA 88
B1 00 60 A2 00 18 65 00 48 8A 65 01 AA 68 60 A9
00 AA A0 00 84 02 84 03 48 20 AB F7 A0 03 A5 03
91 00 88 A5 02 91 00 88 8A 91 00 68 88 91 00 60
D0 06 A2 00 8A 60 D0 FA A2 00 A9 01 60 F0 F9 30
F7 A2 00 8A 60 F0 02 10 EF A2 00 8A 60 F0 E9 90
E7 A2 00 8A 60 F0 DB A2 00 8A 2A 60 A0 00 B1 00
A4 00 F0 07 C6 00 A0 00 91 00 60 C6 01 C6 00 91
00 60 A9 00 A2 00 48 A5 00 38 E9 02 85 00 B0 02
C6 01 A0 01 8A 91 00 68 88 91 00 60 48 84 10 A0
01 B1 00 85 09 88 B1 00 85 08 A4 10 68 91 08 4C
E1 F7 A0 00 91 00 C8 48 8A 91 00 68 60 A9 25 85
08 A9 02 85 09 A9 00 A8 A2 02 F0 0A 91 08 C8 D0
FB E6 09 CA D0 F6 C0 00 F0 05 91 08 C8 D0 F7 60
45 72 72 6F 72 20 69 6E 69 74 20 53 44 20 43 41
52 44 0D 0A 00 53 44 20 43 61 72 64 20 69 6E 69
74 0D 0A 00 53 74 61 72 74 0D 0A 00 6F 70 5F 63
6F 6E 64 20 65 72 72 6F 72 0D 0A 00 49 46 20 43
6F 6E 64 0D 0A 00 47 6F 20 49 44 4C 45 0D 0A 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -254,4 +199,59 @@ CA D0 F6 C0 2C F0 05 91 08 C8 D0 F7 60 41 6E 64
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 A5 F0 30 F0 A6 F0
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 9A F0 25 F0 9B F0

BIN
hw/efinix_fpga/ip/uart/ipm/component.pickle
View File

Binary file not shown.

BIN
hw/efinix_fpga/ip/uart/ipm/graph.pickle
View File

Binary file not shown.

23
hw/efinix_fpga/ip/uart/settings.json
View File

@@ -19,31 +19,16 @@
"ENABLE_PARITY": "1'b0",
"FIX_BAUDRATE": "1'b1",
"PARITY_MODE": "1'b0",
"BOOTUP_CHECK": "1'b1"
"BOOTUP_CHECK": "1'b0"
},
"output": {
"external_source_source": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd"
],
"external_example_example": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/command_state.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/decoder.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/encoder.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/led_ctl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/resets.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_defines.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo_top.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/user_register.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.peri.xml",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.xml",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_timing_T20.sdc",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_define.vh"
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh"
]
},
"sw_version": "2023.1.150",
"generated_date": "2023-07-16T20:20:12.259229"
"generated_date": "2023-07-23T03:23:04.338270"
}

4
hw/efinix_fpga/ip/uart/uart.v
View File

@@ -43,7 +43,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`define IP_UUID _d1961caf8b8d4ca092806671a99095c2
`define IP_UUID _8d7ceb45e0e64e208e634a02f6a59365
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module uart (
@@ -69,7 +69,7 @@ input [7:0] tx_data
.ENABLE_PARITY (1'b0),
.FIX_BAUDRATE (1'b1),
.PARITY_MODE (1'b0),
.BOOTUP_CHECK (1'b1)
.BOOTUP_CHECK (1'b0)
) u_top_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),

2
hw/efinix_fpga/ip/uart/uart_define.vh
View File

@@ -49,4 +49,4 @@ localparam BAUD = 115200;
localparam ENABLE_PARITY = 1'b0;
localparam FIX_BAUDRATE = 1'b1;
localparam PARITY_MODE = 1'b0;
localparam BOOTUP_CHECK = 1'b1;
localparam BOOTUP_CHECK = 1'b0;

448
hw/efinix_fpga/simulation/spi_controller
View File

@@ -1,448 +0,0 @@
#! /usr/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 9;
:vpi_module "/usr/lib64/ivl/system.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/lib64/ivl/va_math.vpi";
:vpi_module "/usr/lib64/ivl/v2009.vpi";
S_0x55defa4f97e0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x55defa4f9970 .scope module, "sim" "sim" 3 1;
.timescale -8 -9;
v0x55defa5217a0_0 .var "_spi_device_data", 7 0;
v0x55defa5218a0_0 .var "clk_50", 0 0;
v0x55defa521960_0 .var "data", 7 0;
v0x55defa521a20_0 .var "i_addr", 1 0;
v0x55defa521ae0_0 .var "i_clk", 0 0;
v0x55defa521bd0_0 .var "i_cs", 0 0;
v0x55defa521c70_0 .var "i_data", 7 0;
v0x55defa521d10_0 .var "i_rst", 0 0;
v0x55defa521db0_0 .var "i_rwb", 0 0;
v0x55defa521e50_0 .var "i_spi_miso", 0 0;
v0x55defa521f20_0 .net "o_data", 7 0, v0x55defa520590_0; 1 drivers
v0x55defa521ff0_0 .net "o_spi_clk", 0 0, L_0x55defa4e9b80; 1 drivers
v0x55defa5220c0_0 .net "o_spi_cs", 0 0, L_0x55defa4e84f0; 1 drivers
v0x55defa522190_0 .net "o_spi_mosi", 0 0, L_0x55defa4e09c0; 1 drivers
E_0x55defa4f0300 .event edge, v0x55defa520670_0;
S_0x55defa4b6270 .scope module, "dut" "spi_controller" 3 22, 4 1 0, S_0x55defa4f9970;
.timescale 0 0;
.port_info 0 /INPUT 1 "i_clk";
.port_info 1 /INPUT 1 "i_rst";
.port_info 2 /INPUT 1 "i_cs";
.port_info 3 /INPUT 1 "i_rwb";
.port_info 4 /INPUT 2 "i_addr";
.port_info 5 /INPUT 8 "i_data";
.port_info 6 /OUTPUT 8 "o_data";
.port_info 7 /OUTPUT 1 "o_spi_cs";
.port_info 8 /OUTPUT 1 "o_spi_clk";
.port_info 9 /OUTPUT 1 "o_spi_mosi";
.port_info 10 /INPUT 1 "i_spi_miso";
L_0x55defa4e84f0 .functor NOT 1, L_0x55defa522260, C4<0>, C4<0>, C4<0>;
L_0x55defa4e9b80 .functor BUFZ 1, v0x55defa520dd0_0, C4<0>, C4<0>, C4<0>;
L_0x55defa4e09c0 .functor BUFZ 1, v0x55defa520d10_0, C4<0>, C4<0>, C4<0>;
v0x55defa4e8690_0 .net *"_ivl_1", 0 0, L_0x55defa522260; 1 drivers
v0x55defa4e9d20_0 .var "active", 0 0;
v0x55defa4e0b20_0 .var "count", 2 0;
v0x55defa4e11c0_0 .net "i_addr", 1 0, v0x55defa521a20_0; 1 drivers
v0x55defa4e14a0_0 .net "i_clk", 0 0, v0x55defa521ae0_0; 1 drivers
v0x55defa4dfca0_0 .net "i_cs", 0 0, v0x55defa521bd0_0; 1 drivers
v0x55defa4e0660_0 .net "i_data", 7 0, v0x55defa521c70_0; 1 drivers
v0x55defa520350_0 .net "i_rst", 0 0, v0x55defa521d10_0; 1 drivers
v0x55defa520410_0 .net "i_rwb", 0 0, v0x55defa521db0_0; 1 drivers
v0x55defa5204d0_0 .net "i_spi_miso", 0 0, v0x55defa521e50_0; 1 drivers
v0x55defa520590_0 .var "o_data", 7 0;
v0x55defa520670_0 .net "o_spi_clk", 0 0, L_0x55defa4e9b80; alias, 1 drivers
v0x55defa520730_0 .net "o_spi_cs", 0 0, L_0x55defa4e84f0; alias, 1 drivers
v0x55defa5207f0_0 .net "o_spi_mosi", 0 0, L_0x55defa4e09c0; alias, 1 drivers
v0x55defa5208b0_0 .var "r_baud_rate", 7 0;
v0x55defa520990_0 .var "r_clock_counter", 8 0;
v0x55defa520a70_0 .var "r_control", 7 0;
v0x55defa520b50_0 .var "r_input_data", 7 0;
v0x55defa520c30_0 .var "r_output_data", 7 0;
v0x55defa520d10_0 .var "r_spi_mosi", 0 0;
v0x55defa520dd0_0 .var "spi_clk", 0 0;
E_0x55defa4f2fe0/0 .event anyedge, v0x55defa4e11c0_0, v0x55defa5208b0_0, v0x55defa520b50_0, v0x55defa4e9d20_0;
E_0x55defa4f2fe0/1 .event anyedge, v0x55defa520a70_0;
E_0x55defa4f2fe0 .event/or E_0x55defa4f2fe0/0, E_0x55defa4f2fe0/1;
E_0x55defa4f1160 .event negedge, v0x55defa4e14a0_0;
L_0x55defa522260 .part v0x55defa520a70_0, 0, 1;
S_0x55defa521050 .scope task, "read_reg" "read_reg" 3 40, 3 40 0, S_0x55defa4f9970;
.timescale -8 -9;
v0x55defa521220_0 .var "_addr", 2 0;
v0x55defa521320_0 .var "_data", 7 0;
E_0x55defa4da3a0 .event posedge, v0x55defa4e14a0_0;
TD_sim.read_reg ;
%wait E_0x55defa4f1160;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521bd0_0, 0;
%load/vec4 v0x55defa521220_0;
%pad/u 2;
%assign/vec4 v0x55defa521a20_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521db0_0, 0;
%pushi/vec4 255, 0, 8;
%assign/vec4 v0x55defa521c70_0, 0;
%wait E_0x55defa4da3a0;
%load/vec4 v0x55defa521f20_0;
%assign/vec4 v0x55defa521320_0, 0;
%wait E_0x55defa4f1160;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa521bd0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521db0_0, 0;
%end;
S_0x55defa521400 .scope task, "write_reg" "write_reg" 3 27, 3 27 0, S_0x55defa4f9970;
.timescale -8 -9;
v0x55defa5215e0_0 .var "_addr", 2 0;
v0x55defa5216c0_0 .var "_data", 7 0;
TD_sim.write_reg ;
%wait E_0x55defa4f1160;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521bd0_0, 0;
%load/vec4 v0x55defa5215e0_0;
%pad/u 2;
%assign/vec4 v0x55defa521a20_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa521db0_0, 0;
%pushi/vec4 255, 0, 8;
%assign/vec4 v0x55defa521c70_0, 0;
%wait E_0x55defa4da3a0;
%load/vec4 v0x55defa5216c0_0;
%assign/vec4 v0x55defa521c70_0, 0;
%wait E_0x55defa4f1160;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa521bd0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521db0_0, 0;
%end;
.scope S_0x55defa4b6270;
T_2 ;
%wait E_0x55defa4f1160;
%load/vec4 v0x55defa520350_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%pushi/vec4 1, 0, 8;
%assign/vec4 v0x55defa5208b0_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x55defa520b50_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x55defa520c30_0, 0;
%pushi/vec4 0, 0, 8;
%assign/vec4 v0x55defa520a70_0, 0;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0x55defa520990_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x55defa4e0b20_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa520dd0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa4e9d20_0, 0;
%jmp T_2.1;
T_2.0 ;
%load/vec4 v0x55defa520410_0;
%inv;
%load/vec4 v0x55defa4dfca0_0;
%and;
%flag_set/vec4 8;
%jmp/0xz T_2.2, 8;
%load/vec4 v0x55defa4e11c0_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_2.4, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_2.5, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_2.6, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_2.7, 6;
%vpi_call/w 4 52 "$warning", "value is unhandled for priority or unique case statement" {0 0 0};
%jmp T_2.8;
T_2.4 ;
%load/vec4 v0x55defa4e0660_0;
%assign/vec4 v0x55defa5208b0_0, 0;
%jmp T_2.8;
T_2.5 ;
%jmp T_2.8;
T_2.6 ;
%load/vec4 v0x55defa4e0660_0;
%assign/vec4 v0x55defa520c30_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa4e9d20_0, 0;
%jmp T_2.8;
T_2.7 ;
%load/vec4 v0x55defa4e0660_0;
%assign/vec4 v0x55defa520a70_0, 0;
%jmp T_2.8;
T_2.8 ;
%pop/vec4 1;
T_2.2 ;
%load/vec4 v0x55defa4e9d20_0;
%flag_set/vec4 8;
%jmp/0xz T_2.9, 8;
%load/vec4 v0x55defa520c30_0;
%parti/s 1, 7, 4;
%assign/vec4 v0x55defa520d10_0, 0;
%load/vec4 v0x55defa520990_0;
%addi 1, 0, 9;
%assign/vec4 v0x55defa520990_0, 0;
%load/vec4 v0x55defa5208b0_0;
%pad/u 9;
%load/vec4 v0x55defa520990_0;
%cmp/u;
%flag_or 5, 4;
%jmp/0xz T_2.11, 5;
%pushi/vec4 0, 0, 9;
%assign/vec4 v0x55defa520990_0, 0;
%load/vec4 v0x55defa520dd0_0;
%inv;
%assign/vec4 v0x55defa520dd0_0, 0;
%load/vec4 v0x55defa520dd0_0;
%cmpi/e 0, 0, 1;
%jmp/0xz T_2.13, 4;
%load/vec4 v0x55defa520c30_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55defa520c30_0, 0;
%load/vec4 v0x55defa4e0b20_0;
%addi 1, 0, 3;
%assign/vec4 v0x55defa4e0b20_0, 0;
T_2.13 ;
%load/vec4 v0x55defa520dd0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_2.15, 4;
%load/vec4 v0x55defa520b50_0;
%parti/s 7, 0, 2;
%load/vec4 v0x55defa5204d0_0;
%concat/vec4; draw_concat_vec4
%assign/vec4 v0x55defa520b50_0, 0;
%load/vec4 v0x55defa4e0b20_0;
%cmpi/e 0, 0, 3;
%jmp/0xz T_2.17, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa4e9d20_0, 0;
T_2.17 ;
T_2.15 ;
T_2.11 ;
T_2.9 ;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_0x55defa4b6270;
T_3 ;
Ewait_0 .event/or E_0x55defa4f2fe0, E_0x0;
%wait Ewait_0;
%load/vec4 v0x55defa4e11c0_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_3.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_3.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_3.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_3.3, 6;
%vpi_call/w 4 88 "$warning", "value is unhandled for priority or unique case statement" {0 0 0};
%jmp T_3.4;
T_3.0 ;
%load/vec4 v0x55defa5208b0_0;
%store/vec4 v0x55defa520590_0, 0, 8;
%jmp T_3.4;
T_3.1 ;
%load/vec4 v0x55defa520b50_0;
%store/vec4 v0x55defa520590_0, 0, 8;
%jmp T_3.4;
T_3.2 ;
%jmp T_3.4;
T_3.3 ;
%load/vec4 v0x55defa4e9d20_0;
%load/vec4 v0x55defa520a70_0;
%parti/s 7, 0, 2;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x55defa520590_0, 0, 8;
%jmp T_3.4;
T_3.4 ;
%pop/vec4 1;
%jmp T_3;
.thread T_3, $push;
.scope S_0x55defa4f9970;
T_4 ;
%delay 10, 0;
%load/vec4 v0x55defa5218a0_0;
%pushi/vec4 0, 0, 1;
%cmp/e;
%flag_get/vec4 6;
%store/vec4 v0x55defa5218a0_0, 0, 1;
%jmp T_4;
.thread T_4;
.scope S_0x55defa4f9970;
T_5 ;
%delay 1000, 0;
%load/vec4 v0x55defa521ae0_0;
%pushi/vec4 0, 0, 1;
%cmp/e;
%flag_get/vec4 6;
%store/vec4 v0x55defa521ae0_0, 0, 1;
%jmp T_5;
.thread T_5;
.scope S_0x55defa4f9970;
T_6 ;
%vpi_call/w 3 55 "$dumpfile", "spi_controller.vcd" {0 0 0};
%vpi_call/w 3 56 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x55defa4f9970 {0 0 0};
%end;
.thread T_6;
.scope S_0x55defa4f9970;
T_7 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521d10_0, 0;
%pushi/vec4 5, 0, 32;
T_7.0 %dup/vec4;
%pushi/vec4 0, 0, 32;
%cmp/s;
%jmp/1xz T_7.1, 5;
%jmp/1 T_7.1, 4;
%pushi/vec4 1, 0, 32;
%sub;
%wait E_0x55defa4da3a0;
%jmp T_7.0;
T_7.1 ;
%pop/vec4 1;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa521bd0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55defa521db0_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x55defa521a20_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55defa521d10_0, 0;
%pushi/vec4 5, 0, 32;
T_7.2 %dup/vec4;
%pushi/vec4 0, 0, 32;
%cmp/s;
%jmp/1xz T_7.3, 5;
%jmp/1 T_7.3, 4;
%pushi/vec4 1, 0, 32;
%sub;
%wait E_0x55defa4da3a0;
%jmp T_7.2;
T_7.3 ;
%pop/vec4 1;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55defa5215e0_0, 0, 3;
%pushi/vec4 1, 0, 8;
%store/vec4 v0x55defa5216c0_0, 0, 8;
%fork TD_sim.write_reg, S_0x55defa521400;
%join;
%pushi/vec4 2, 0, 3;
%store/vec4 v0x55defa5215e0_0, 0, 3;
%pushi/vec4 170, 0, 8;
%store/vec4 v0x55defa5216c0_0, 0, 8;
%fork TD_sim.write_reg, S_0x55defa521400;
%join;
%pushi/vec4 128, 0, 8;
%store/vec4 v0x55defa521960_0, 0, 8;
T_7.4 ;
%load/vec4 v0x55defa521960_0;
%pad/u 32;
%pushi/vec4 128, 0, 32;
%and;
%or/r;
%flag_set/vec4 8;
%jmp/0xz T_7.5, 8;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55defa521220_0, 0, 3;
%fork TD_sim.read_reg, S_0x55defa521050;
%join;
%load/vec4 v0x55defa521320_0;
%store/vec4 v0x55defa521960_0, 0, 8;
%jmp T_7.4;
T_7.5 ;
%pushi/vec4 3, 0, 3;
%store/vec4 v0x55defa5215e0_0, 0, 3;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x55defa5216c0_0, 0, 8;
%fork TD_sim.write_reg, S_0x55defa521400;
%join;
%pushi/vec4 1, 0, 3;
%store/vec4 v0x55defa521220_0, 0, 3;
%fork TD_sim.read_reg, S_0x55defa521050;
%join;
%load/vec4 v0x55defa521320_0;
%store/vec4 v0x55defa521960_0, 0, 8;
%load/vec4 v0x55defa521960_0;
%cmpi/e 85, 0, 8;
%jmp/0xz T_7.6, 4;
%jmp T_7.7;
T_7.6 ;
%vpi_call/w 3 79 "$error" {0 0 0};
T_7.7 ;
%pushi/vec4 50, 0, 32;
T_7.8 %dup/vec4;
%pushi/vec4 0, 0, 32;
%cmp/s;
%jmp/1xz T_7.9, 5;
%jmp/1 T_7.9, 4;
%pushi/vec4 1, 0, 32;
%sub;
%wait E_0x55defa4da3a0;
%jmp T_7.8;
T_7.9 ;
%pop/vec4 1;
%vpi_call/w 3 83 "$finish" {0 0 0};
%end;
.thread T_7;
.scope S_0x55defa4f9970;
T_8 ;
%pushi/vec4 85, 0, 8;
%assign/vec4 v0x55defa5217a0_0, 0;
%end;
.thread T_8;
.scope S_0x55defa4f9970;
T_9 ;
%wait E_0x55defa4f0300;
%load/vec4 v0x55defa5220c0_0;
%cmpi/e 0, 0, 1;
%jmp/0xz T_9.0, 4;
%load/vec4 v0x55defa521ff0_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_9.2, 4;
%load/vec4 v0x55defa5217a0_0;
%parti/s 1, 7, 4;
%assign/vec4 v0x55defa521e50_0, 0;
T_9.2 ;
%load/vec4 v0x55defa521ff0_0;
%cmpi/e 0, 0, 1;
%jmp/0xz T_9.4, 4;
%load/vec4 v0x55defa5217a0_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%assign/vec4 v0x55defa5217a0_0, 0;
T_9.4 ;
T_9.0 ;
%jmp T_9;
.thread T_9;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"-";
"spi_controller_tb.sv";
"../spi_controller.sv";

4
hw/efinix_fpga/simulation/spi_controller_tb.sv
View File

@@ -69,7 +69,7 @@ initial begin
repeat(5) @(posedge i_clk);
write_reg(3, 1);
write_reg(2, 8'hAA);
write_reg(2, 8'hFF);
data = (1 << 7);
while(data & (1 << 7)) begin
read_reg(3, data);
@@ -99,4 +99,4 @@ always @(edge o_spi_clk) begin
end
end
endmodule
endmodule

22
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sun Jul 16 13:10:02 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sat Jul 22 17:30:06 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -306,21 +306,17 @@
<efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="sd_clk" gpio_def="GPIOL_26" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="sd_clk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="sd_cmd" gpio_def="GPIOL_25" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="sd_cmd_IN" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="weak pullup" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="sd_cmd_OUT" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="sd_cmd_OE" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="sd_cs" gpio_def="GPIOL_36" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="sd_cs" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="sd_data" gpio_def="GPIOL_29" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="sd_data_IN" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="weak pullup" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="sd_data_OUT" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:output_enable_config name="sd_data_OE" is_register="false" clock_name="" is_clock_inverted="false"/>
<efxpt:gpio name="spi_clk" gpio_def="GPIOL_26" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="spi_clk" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="spi_miso" gpio_def="GPIOL_29" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="spi_miso" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="spi_mosi" gpio_def="GPIOL_25" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="spi_mosi" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="uart_rx" gpio_def="GPIOL_11" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="uart_rx" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>

69
hw/efinix_fpga/super6502.sv
View File

@@ -41,30 +41,12 @@ module super6502
output uart_tx,
output sd_cs,
output sd_clk,
input sd_cmd_IN,
output sd_cmd_OUT,
output sd_cmd_OE,
input sd_data_IN,
output sd_data_OUT,
output sd_data_OE
output spi_clk,
output spi_mosi,
input spi_miso
);
assign sd_cs = '1;
logic o_sd_cmd, i_sd_cmd;
logic o_sd_data, i_sd_data;
assign i_sd_cmd = sd_cmd_IN;
assign sd_cmd_OUT = '0;
assign sd_cmd_OE = ~o_sd_cmd;
assign i_sd_data = sd_data_IN;
assign sd_data_OUT = '0;
assign sd_data_OE = ~o_sd_data;
assign pll_cpu_reset = '1;
assign o_pll_reset = '1;
@@ -97,7 +79,7 @@ logic w_timer_cs;
logic w_multiplier_cs;
logic w_divider_cs;
logic w_uart_cs;
logic w_sdcard_cs;
logic w_spi_cs;
addr_decode u_addr_decode(
.i_addr(cpu_addr),
@@ -107,7 +89,7 @@ addr_decode u_addr_decode(
.o_multiplier_cs(w_multiplier_cs),
.o_divider_cs(w_divider_cs),
.o_uart_cs(w_uart_cs),
.o_sdcard_cs(w_sdcard_cs),
.o_spi_cs(w_spi_cs),
.o_sdram_cs(w_sdram_cs)
);
@@ -117,7 +99,7 @@ logic [7:0] w_timer_data_out;
logic [7:0] w_multiplier_data_out;
logic [7:0] w_divider_data_out;
logic [7:0] w_uart_data_out;
logic [7:0] w_sdcard_data_out;
logic [7:0] w_spi_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
@@ -133,8 +115,8 @@ always_comb begin
cpu_data_out = w_divider_data_out;
else if (w_uart_cs)
cpu_data_out = w_uart_data_out;
else if (w_sdcard_cs)
cpu_data_out = w_sdcard_data_out;
else if (w_spi_cs)
cpu_data_out = w_spi_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else
@@ -206,28 +188,19 @@ uart_wrapper u_uart(
.irqb(w_uart_irqb)
);
logic sd_clk;
always @(posedge clk_2) begin
sd_clk <= ~sd_clk;
end
spi_controller spi_controller(
.i_clk(clk_2),
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr[1:0]),
.i_data(cpu_data_in),
.o_data(w_spi_data_out),
sd_controller sd_controller(
.clk(clk_2),
.sd_clk(sd_clk),
.rst(rst),
.addr(cpu_addr[2:0]),
.data(cpu_data_in),
.cs(w_sdcard_cs),
.rw(cpu_rwb),
.i_sd_cmd(i_sd_cmd),
.o_sd_cmd(o_sd_cmd),
.i_sd_data(i_sd_data),
.o_sd_data(o_sd_data),
.data_out(w_sdcard_data_out)
.o_spi_cs(sd_cs),
.o_spi_clk(spi_clk),
.o_spi_mosi(spi_mosi),
.i_spi_miso(spi_miso)
);

7
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Wed July 19 2023 21:04:26" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Sun July 23 2023 14:51:17" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -19,6 +19,7 @@
<efx:design_file name="sd_controller.sv" version="default" library="default"/>
<efx:design_file name="crc7.sv" version="default" library="default"/>
<efx:design_file name="rom.sv" version="default" library="default"/>
<efx:design_file name="spi_controller.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
@@ -62,11 +63,11 @@
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="include" value="ip/divider" value_type="e_string"/>
<efx:param name="include" value="ip/uart" value_type="e_string"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>