From 5e03795c0958a88e65f21bd100aac83f8d201757 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 21 Sep 2023 23:22:17 -0700
Subject: [PATCH] Get something simulated

Infinite loop being caused somewhere
---
 hw/efinix_fpga/simulation/Makefile       |  9 ++-
 hw/efinix_fpga/simulation/src/sim_top.sv | 93 +++++++++++++++++++++++-
 2 files changed, 98 insertions(+), 4 deletions(-)

diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index bd842ad..0385b34 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -8,10 +8,15 @@ INC=$(shell find include/ -type f)
 
 TOP_MODULE=sim_top
 TARGET=sim_top
+INIT_MEM=init_hex.mem
 
-all: 
+all: $(INIT_MEM)
 	iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
+$(INIT_MEM):
+	cp ../$(INIT_MEM) .
+
 .PHONY: clean
 clean:
-	rm -rf $(TARGET)
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+	rm -rf $(TARGET)
+	rm $(INIT_MEM)
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diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index c20fa0f..6f45efe 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -1,10 +1,99 @@
+`timescale 1ns/1ps
+
 module sim_top();
 
+logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
+
+// clk_100
+initial begin
+	r_sysclk <= '0;
+	forever begin
+		#5 r_sysclk <= ~r_sysclk;
+	end
+end
+
+// clk_200
+initial begin
+	r_sdrclk <= '0;
+	forever begin
+		#2.5 r_sdrclk <= ~r_sdrclk;
+	end
+end
+
+// clk_50
+initial begin
+	r_clk_50 <= '0;
+	forever begin
+		#10 r_clk_50 <= ~r_clk_50;
+	end
+end
+
+// clk_2
+initial begin
+	r_clk_2 <= '0;
+	forever begin
+		#250 r_clk_2 <= ~r_clk_2;
+	end
+end
+
+initial begin
+    $dumpfile("sim_top.vcd");
+    $dumpvars(0,sim_top);
+end
+
+logic button_reset;
+
+initial begin
+	button_reset <= '0;
+	repeat(10) @(r_clk_2);
+	button_reset <= '1;
+	repeat(2000) @(r_clk_2);
+	$finish();
+end
+
+logic w_cpu_reset;
+logic [15:0] w_cpu_addr;
+logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
+logic cpu_rwb;
+
 //TODO: this
-cpu_65c02 u_cpu();
+cpu_65c02 u_cpu(
+	.clk(r_clk_2),
+	// .reset(~w_cpu_reset),
+	.reset(~button_reset),
+	.AB(w_cpu_addr),
+	.RDY('1),
+	.IRQ('0),
+	.NMI('0),
+	.DI(w_cpu_data_from_dut),
+	// .DO(w_cpu_data_from_cpu),
+	.WE(cpu_rwb)
+);
+
+
+// Having the super6502 causes an infinite loop,
+// but just the rom works. Need to whittle down
+// which block is causing it.
+rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
+    .addr(w_cpu_addr[11:0]),
+    .clk(r_clk_2),
+    .data(w_cpu_data_from_dut)
+);
 
 //TODO: also this
-super6502 u_dut();
+// super6502 u_dut(
+// 	.i_sysclk(r_sysclk),
+// 	.i_sdrclk(r_sdrclk),
+// 	.i_tACclk(r_sdrclk),
+// 	.clk_50(r_clk_50),
+// 	.clk_2(r_clk_2),
+// 	.button_reset(button_reset),
+// 	.cpu_resb(w_cpu_reset),
+// 	.cpu_addr(w_cpu_addr),
+// 	.cpu_data_out(w_cpu_data_from_dut),
+// 	// .cpu_data_in(w_cpu_data_from_cpu),
+// 	.cpu_rwb(~cpu_rwb)
+// );
 
 
 endmodule
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