bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add code testbench

Browse Source
This commit is contained in:
Byron Lathi
2023-10-21 17:06:23 -07:00
parent 4b415ed2ba
commit 5f863c9857
3 changed files with 212 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
hw/efinix_fpga/simulation/Makefile
View File

@@ -32,6 +32,9 @@ full_sim: $(TARGET) $(SD_IMAGE)
mapper_tb: $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)