From 5fc71567f2db0fbcd0729597a677a3ff3938e8ba Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Wed, 6 Sep 2023 20:18:36 -0700
Subject: [PATCH] Add basic mapping

---
 hw/efinix_fpga/mapper.sv     | 19 ++++++++++++++++++-
 hw/efinix_fpga/super6502.sv  |  2 +-
 hw/efinix_fpga/super6502.xml |  2 +-
 3 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/efinix_fpga/mapper.sv b/hw/efinix_fpga/mapper.sv
index 4bf88fb..0c75cf9 100644
--- a/hw/efinix_fpga/mapper.sv
+++ b/hw/efinix_fpga/mapper.sv
@@ -6,7 +6,7 @@ module mapper(
     output logic [24:0] sdram_addr,
 
     input cs,
-    input rw,
+    input rwb,
 
     input [7:0] i_data,
     output logic [7:0] o_data
@@ -23,12 +23,29 @@ logic en;
 always_comb begin
     if (!en) begin
         sdram_addr = {9'b0, cpu_addr};
+    end else begin
+        sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
     end
 end
 
 always_ff @(posedge clk) begin
     if (rst) begin
         en <= '0;
+        for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
+            map[a] = a;
+        end
+    end else begin
+        if (~rwb & cs) begin
+            if (base_addr == 16'h32) begin
+                en <= i_data[0];
+            end else begin
+                if (!base_addr[0]) begin
+                    map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
+                end else begin
+                    map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
+                end
+            end
+        end
     end
 end
 
diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv
index 1ac44d8..c00146f 100644
--- a/hw/efinix_fpga/super6502.sv
+++ b/hw/efinix_fpga/super6502.sv
@@ -216,7 +216,7 @@ mapper u_mapper(
     .cpu_addr(cpu_addr),
     .sdram_addr(w_sdram_addr),
     .cs(w_mapper_cs),
-    .rw(cpu_rwb),
+    .rwb(cpu_rwb),
     .i_data(cpu_data_in),
     .o_data(w_mapper_data_out)
 );
diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml
index aaabab3..5df8475 100644
--- a/hw/efinix_fpga/super6502.xml
+++ b/hw/efinix_fpga/super6502.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Wed September 6 2023 19:46:49" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Wed September 6 2023 20:09:59" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>