From 61f6e53327802db2981b363f4ad08aabd8045b6a Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 10 Mar 2024 21:57:22 -0700
Subject: [PATCH] Updates based on fpga test

1. in SD mode, CMD0 does not have a response, so we specifically ignore
   it.

2. The penable signal was messed up, although it looks like this doesn't
   matter anyway

3. The SD clock should be out of phase from the data signal by 180
   degrees, so that we get max hold time
---
 hw/super6502_fpga/src/sub/rtl-common    |  2 +-
 hw/super6502_fpga/src/sub/sd_controller |  2 +-
 sw/test_code/sd_controller_test/main.s  | 11 +++++++++++
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common
index a780aab..bb214bc 160000
--- a/hw/super6502_fpga/src/sub/rtl-common
+++ b/hw/super6502_fpga/src/sub/rtl-common
@@ -1 +1 @@
-Subproject commit a780aab98b217c6d4750a6b7278902e8a7d070e2
+Subproject commit bb214bc79ee665325adb423472a13dbeec4431ed
diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller
index fc2813b..091984c 160000
--- a/hw/super6502_fpga/src/sub/sd_controller
+++ b/hw/super6502_fpga/src/sub/sd_controller
@@ -1 +1 @@
-Subproject commit fc2813b809e2fd25e0ce55e73aad9ce05cb603fb
+Subproject commit 091984c3342f13cfbf50c63f1fead7febc49158e
diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s
index ac93719..b497f15 100644
--- a/sw/test_code/sd_controller_test/main.s
+++ b/sw/test_code/sd_controller_test/main.s
@@ -7,6 +7,7 @@
 .addr      _irq_int    ; IRQ/BRK vector
 
 SD_CONTROLLER = $e000
+SD_ARG = SD_CONTROLLER + $4
 CLK_DIV = $20
 
 .code
@@ -15,6 +16,16 @@ _nmi_int:
 _irq_int:
 
 _init:
+        lda #$00
+        sta SD_CONTROLLER
+
+        lda #$aa
+        sta SD_ARG
+        lda #$01
+        sta SD_ARG+1
+        lda #$00
+        sta SD_ARG+2
+        sta SD_ARG+3
         lda #$08
         sta SD_CONTROLLER