Updates based on fpga test

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1. in SD mode, CMD0 does not have a response, so we specifically ignore
   it.

2. The penable signal was messed up, although it looks like this doesn't
   matter anyway

3. The SD clock should be out of phase from the data signal by 180
   degrees, so that we get max hold time

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This commit is contained in:

Byron Lathi

2024-03-10 21:57:22 -07:00

parent 3c0bf9740c

commit 61f6e53327

3 changed files with 13 additions and 2 deletions

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2

hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: a780aab98b...bb214bc79e

2

hw/super6502_fpga/src/sub/sd_controller

Submodule hw/super6502_fpga/src/sub/sd_controller updated: fc2813b809...091984c334