Resolve "Add build check to CI"

hw/efinix_fpga/simulation/Makefile

@@ -5,9 +5,10 @@ SRCS+=$(shell find ../src/ -type f -name "*.*v")
 INC=$(shell find include/ -type f)
 
 TEST_PROGRAM_NAME?=loop_test
-
+TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
+
 #TODO implement something like sources.list
 
 TOP_MODULE=sim_top
@@ -19,9 +20,10 @@ all: $(INIT_MEM)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
 $(INIT_MEM):
+	$(MAKE) -C $(TEST_FOLDER)
 	cp $(TEST_PROGRAM) ./init_hex.mem
 
 .PHONY: clean
 clean:
 	rm -rf $(TARGET)
-	rm -rf $(INIT_MEM)
+	rm -rf $(INIT_MEM)