From aa337c61d520e5bc333fe9691bc4f998651201dc Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 15 Mar 2022 23:45:57 -0500 Subject: [PATCH 1/9] Create sdram platform --- hw/fpga/.gitignore | 4 +- hw/fpga/sdram_platform.qsys | 334 +++ hw/fpga/sdram_platform.sopcinfo | 4221 +++++++++++++++++++++++++++++++ 3 files changed, 4557 insertions(+), 2 deletions(-) create mode 100644 hw/fpga/sdram_platform.qsys create mode 100644 hw/fpga/sdram_platform.sopcinfo diff --git a/hw/fpga/.gitignore b/hw/fpga/.gitignore index fb6b042..52da622 100644 --- a/hw/fpga/.gitignore +++ b/hw/fpga/.gitignore @@ -23,8 +23,6 @@ # design. # Need to keep all HDL files -# *.vhd -# *.v # Don't keep signal tap files. *.stp @@ -71,5 +69,7 @@ greybox_tmp/ incremental_db/ db/ output_files/ +.qsys_edit/ +sdram_platform/ PLLJ_PLLSPE_INFO.txt diff --git a/hw/fpga/sdram_platform.qsys b/hw/fpga/sdram_platform.qsys new file mode 100644 index 0000000..6e69912 --- /dev/null +++ b/hw/fpga/sdram_platform.qsys @@ -0,0 +1,334 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + single_Micron_MT48LC4M32B2_7_chip + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED + altpll_avalon_elaboration + altpll_avalon_post_edit + IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} + + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1647404711238322.mif PT#ACTIVECLK_CHECK 0 + UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/fpga/sdram_platform.sopcinfo b/hw/fpga/sdram_platform.sopcinfo new file mode 100644 index 0000000..8591e4a --- /dev/null +++ b/hw/fpga/sdram_platform.sopcinfo @@ -0,0 +1,4221 @@ + + + + + + + java.lang.Integer + 1647405925 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C7G + false + true + false + true + DEVICE + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + ext_bridge + clk + ext_bridge.clk + + + false + sdram_pll + inclk_interface + sdram_pll.inclk_interface + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + int + 64 + false + true + true + true + + + java.lang.String + Mbytes + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + avalon_readdata + Input + 8 + readdata + + + avalon_waitrequest + Input + 1 + waitrequest + + + avalon_byteenable + Output + 1 + byteenable + + + avalon_read + Output + 1 + read + + + avalon_write + Output + 1 + write + + + avalon_writedata + Output + 8 + writedata + + + avalon_address + Output + 26 + address + + + false + sdram + s1 + sdram.s1 + 0 + 67108864 + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + address + Input + 26 + export + + + byte_enable + Input + 1 + export + + + read + Input + 1 + export + + + write + Input + 1 + export + + + write_data + Input + 8 + export + + + acknowledge + Output + 1 + export + + + read_data + Output + 8 + export + + + + + + + embeddedsw.CMacro.CAS_LATENCY + 3 + + + embeddedsw.CMacro.CONTENTS_INFO + + + + embeddedsw.CMacro.INIT_NOP_DELAY + 0.0 + + + embeddedsw.CMacro.INIT_REFRESH_COMMANDS + 2 + + + embeddedsw.CMacro.IS_INITIALIZED + 1 + + + embeddedsw.CMacro.POWERUP_DELAY + 200.0 + + + embeddedsw.CMacro.REFRESH_PERIOD + 15.625 + + + embeddedsw.CMacro.REGISTER_DATA_IN + 1 + + + embeddedsw.CMacro.SDRAM_ADDR_WIDTH + 25 + + + embeddedsw.CMacro.SDRAM_BANK_WIDTH + 2 + + + embeddedsw.CMacro.SDRAM_COL_WIDTH + 10 + + + embeddedsw.CMacro.SDRAM_DATA_WIDTH + 16 + + + embeddedsw.CMacro.SDRAM_NUM_BANKS + 4 + + + embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS + 1 + + + embeddedsw.CMacro.SDRAM_ROW_WIDTH + 13 + + + embeddedsw.CMacro.SHARED_DATA + 0 + + + embeddedsw.CMacro.SIM_MODEL_BASE + 0 + + + embeddedsw.CMacro.STARVATION_INDICATOR + 0 + + + embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE + "" + + + embeddedsw.CMacro.T_AC + 5.4 + + + embeddedsw.CMacro.T_MRD + 3 + + + embeddedsw.CMacro.T_RCD + 20.0 + + + embeddedsw.CMacro.T_RFC + 70.0 + + + embeddedsw.CMacro.T_RP + 20.0 + + + embeddedsw.CMacro.T_WR + 14.0 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 16 + + + double + 5.4 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 70.0 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 14.0 + false + true + true + true + + + int + 3 + false + true + true + true + + + int + 10 + false + true + true + true + + + int + 16 + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 2 + false + true + true + true + + + java.lang.String + single_Micron_MT48LC4M32B2_7_chip + false + true + false + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + double + 200.0 + false + true + true + true + + + double + 15.625 + false + true + true + true + + + int + 13 + false + true + true + true + + + int + 0 + false + false + false + true + + + long + 3 + false + true + false + true + + + double + 0.0 + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + sdram_platform_sdram + false + true + false + true + UNIQUE_ID + + + long + 67108864 + true + true + false + true + + + int + 25 + true + true + false + true + + + int + 2 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 67108864 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 7 + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + az_addr + Input + 25 + address + + + az_be_n + Input + 2 + byteenable_n + + + az_cs + Input + 1 + chipselect + + + az_data + Input + 16 + writedata + + + az_rd_n + Input + 1 + read_n + + + az_wr_n + Input + 1 + write_n + + + za_data + Output + 16 + readdata + + + za_valid + Output + 1 + readdatavalid + + + za_waitrequest + Output + 1 + waitrequest + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + zs_addr + Output + 13 + export + + + zs_ba + Output + 2 + export + + + zs_cas_n + Output + 1 + export + + + zs_cke + Output + 1 + export + + + zs_cs_n + Output + 1 + export + + + zs_dq + Bidir + 16 + export + + + zs_dqm + Output + 2 + export + + + zs_ras_n + Output + 1 + export + + + zs_we_n + Output + 1 + export + + + + + + + java.lang.String + altpll_avalon_elaboration + false + true + false + true + + + java.lang.String + altpll_avalon_post_edit + false + true + false + true + + + java.lang.String + MAX 10 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 20000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NORMAL + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CLK0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + -1000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NO + false + true + true + true + + + java.lang.String + CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED + false + true + false + true + + + java.lang.String + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1647404711238322.mif PT#ACTIVECLK_CHECK 0 + false + true + false + true + + + java.lang.String + UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + false + true + false + true + + + java.lang.String + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + false + true + false + true + + + java.lang.String + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + false + true + false + true + + + java.lang.String + IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} + false + true + false + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + inclk_interface + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + inclk_interface + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isMemoryDevice + false + + + embeddedsw.configuration.isNonVolatileStorage + false + + + embeddedsw.configuration.isPrintableDevice + false + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + inclk_interface + false + true + true + true + + + java.lang.String + inclk_interface_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + read + Input + 1 + read + + + write + Input + 1 + write + + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c0 + Output + 1 + clk + + + false + sdram + clk + sdram.clk + + + + + + java.lang.String + + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c1 + Output + 1 + clk + + + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + ext_bridge + avalon_master + sdram + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + sdram_pll + c0 + sdram + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + ext_bridge + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + sdram_pll + inclk_interface + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + sdram_pll + inclk_interface_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + sdram + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + ext_bridge + reset + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 18.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 18.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 18.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 18.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 18.1 + + + 1 + altera_up_external_bus_to_avalon_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + External Bus to Avalon Bridge + 18.0 + + + 3 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 18.1 + + + 3 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 18.1 + + + 1 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 18.1 + + + 2 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 18.1 + + + 1 + altera_avalon_new_sdram_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + SDRAM Controller Intel FPGA IP + 18.1 + + + 2 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 18.1 + + + 1 + altpll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + ALTPLL Intel FPGA IP + 18.1 + + + 2 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 18.1 + + + 1 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 18.1 + + + 3 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 18.1 + + + 3 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 18.1 + + 18.1 625 + + From 15e3ae9688bfb86dd0054f46cfca845258d68a59 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 13:31:56 -0500 Subject: [PATCH 2/9] Add SDRAM controller (controller) Turns out there are some issues with holding the chip select for the SDRAM controller high for too long, so there is a simple 2-state fsm which ensures that the chip select is only held for 1 clock cycle for writes and for as long as it takes to read the data from sdram for reads. --- hw/fpga/addr_decode.sv | 6 ++- hw/fpga/sdram_platform.qsys | 4 +- hw/fpga/super6502.qsf | 104 +++++++++++++++++++++++++++++++----- hw/fpga/super6502.sdc | 27 ++++++++-- hw/fpga/super6502.sv | 71 +++++++++++++++++++++++- 5 files changed, 191 insertions(+), 21 deletions(-) diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv index 8d7da6a..c791668 100644 --- a/hw/fpga/addr_decode.sv +++ b/hw/fpga/addr_decode.sv @@ -1,14 +1,16 @@ module addr_decode( input logic [15:0] addr, output logic ram_cs, + output logic sdram_cs, output logic rom_cs, output logic hex_cs, output logic uart_cs, output logic irq_cs ); -assign rom_cs = addr[15]; -assign ram_cs = ~addr[15] && addr < 16'h7ff0; +assign rom_cs = addr >= 16'h8000; +assign ram_cs = addr < 16'h4000; +assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0; assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4; assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6; assign irq_cs = addr == 16'h7fff; diff --git a/hw/fpga/sdram_platform.qsys b/hw/fpga/sdram_platform.qsys index 6e69912..ec790f6 100644 --- a/hw/fpga/sdram_platform.qsys +++ b/hw/fpga/sdram_platform.qsys @@ -6,7 +6,7 @@ version="1.0" description="" tags="INTERNAL_COMPONENT=true" - categories="" /> + categories="System" /> - + diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index 258c17c..55f3a8e 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -188,7 +188,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sob set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cpu_sync set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50 set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp set_location_assignment PIN_F20 -to HEX4[6] set_location_assignment PIN_F19 -to HEX4[5] set_location_assignment PIN_H19 -to HEX4[4] @@ -205,17 +205,6 @@ set_location_assignment PIN_F18 -to HEX4[0] set_location_assignment PIN_E20 -to HEX4[1] set_location_assignment PIN_AB5 -to UART_RXD set_location_assignment PIN_AB6 -to UART_TXD -set_global_assignment -name SYSTEMVERILOG_FILE uart.sv -set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv -set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv -set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv -set_global_assignment -name QIP_FILE ram.qip -set_global_assignment -name SDC_FILE super6502.sdc -set_global_assignment -name QIP_FILE rom.qip -set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv -set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv -set_global_assignment -name QIP_FILE cpu_clk.qip -set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] @@ -283,4 +272,95 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[9] set_location_assignment PIN_A7 -to button_1 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to button_1 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_global_assignment -name QIP_FILE sdram_platform/synthesis/sdram_platform.qip +set_global_assignment -name SYSTEMVERILOG_FILE uart.sv +set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv +set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv +set_global_assignment -name QIP_FILE ram.qip +set_global_assignment -name SDC_FILE super6502.sdc +set_global_assignment -name QIP_FILE rom.qip +set_global_assignment -name SYSTEMVERILOG_FILE HexDriver.sv +set_global_assignment -name SYSTEMVERILOG_FILE SevenSeg.sv +set_global_assignment -name QIP_FILE cpu_clk.qip +set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hw/fpga/super6502.sdc b/hw/fpga/super6502.sdc index 1e1dc19..b6b8652 100644 --- a/hw/fpga/super6502.sdc +++ b/hw/fpga/super6502.sdc @@ -1,11 +1,30 @@ #************************************************************** # Create Clock (where ‘clk’ is the user-defined system clock name) #************************************************************** -create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk}] +create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk_50}] + +create_generated_clock -source [get_pins {u0|sdram_pll|sd1|pll7|clk[1] }] \ + -name clk_dram_ext [get_ports {DRAM_CLK}] + +derive_pll_clocks + # Constrain the input I/O path -set_input_delay -clock {clk} -max 3 [all_inputs] -set_input_delay -clock {clk} -min 2 [all_inputs] +# set_input_delay -clock {clk} -max 3 [all_inputs] +# set_input_delay -clock {clk} -min 2 [all_inputs] # Constrain the output I/O path -set_output_delay -clock {clk} 2 [all_outputs] +#set_output_delay -clock {clk} 2 [all_outputs] derive_clock_uncertainty + +set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*] +set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*] + + +set_multicycle_path -from [get_clocks {clk_dram_ext}] \ + -to [get_clocks {u0|sdram_pll|sd1|pll7|clk[0] }] \ + -setup 2 + +set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}] +set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}] +set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}] +set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}] \ No newline at end of file diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index af0eae9..073a06d 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -24,7 +24,20 @@ module super6502( output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, input logic UART_RXD, - output logic UART_TXD + output logic UART_TXD, + + ///////// SDRAM ///////// + output DRAM_CLK, + output DRAM_CKE, + output [12: 0] DRAM_ADDR, + output [ 1: 0] DRAM_BA, + inout [15: 0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_UDQM, + output DRAM_CS_N, + output DRAM_WE_N, + output DRAM_CAS_N, + output DRAM_RAS_N ); logic rst; @@ -41,10 +54,12 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z; logic [7:0] rom_data_out; logic [7:0] ram_data_out; +logic [7:0] sdram_data_out; logic [7:0] uart_data_out; logic [7:0] irq_data_out; logic ram_cs; +logic sdram_cs; logic rom_cs; logic hex_cs; logic uart_cs; @@ -69,6 +84,7 @@ assign cpu_irqb = irq_data_out == 0; addr_decode decode( .addr(cpu_addr), .ram_cs(ram_cs), + .sdram_cs(sdram_cs), .rom_cs(rom_cs), .hex_cs(hex_cs), .uart_cs(uart_cs), @@ -79,6 +95,8 @@ addr_decode decode( always_comb begin if (ram_cs) cpu_data_out = ram_data_out; + else if (sdram_cs) + cpu_data_out = sdram_data_out; else if (rom_cs) cpu_data_out = rom_data_out; else if (uart_cs) @@ -89,7 +107,58 @@ always_comb begin cpu_data_out = 'x; end +enum logic {S_0, S_1 } teststate, next_teststate; +logic ack; +logic write; +logic _sdram_cs; +always @(posedge clk_50) begin + if (rst) + teststate <= S_0; + else + teststate <= next_teststate; +end + +always_comb begin + next_teststate = teststate; + write = '0; + _sdram_cs = '0; + case (teststate) + S_0: begin + write = sdram_cs & ~cpu_rwb & cpu_phi2; + _sdram_cs = sdram_cs & cpu_phi2; + if (sdram_cs & ~cpu_rwb & ack) + next_teststate = S_1; + end + S_1: begin + if (~(sdram_cs & ~cpu_rwb)) + next_teststate = S_0; + end + endcase +end + +sdram_platform u0 ( + .clk_clk (clk_50), // clk.clk + .reset_reset_n (1'b1), // reset.reset_n + .ext_bus_address (cpu_addr), // ext_bus.address + .ext_bus_byte_enable (1'b1), // .byte_enable + .ext_bus_read (_sdram_cs & cpu_rwb), // .read + .ext_bus_write (write), // .write + .ext_bus_write_data (cpu_data_in), // .write_data + .ext_bus_acknowledge (ack), // .acknowledge + .ext_bus_read_data (sdram_data_out), // .read_data + //SDRAM + .sdram_clk_clk(DRAM_CLK), //clk_sdram.clk + .sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr + .sdram_wire_ba(DRAM_BA), //.ba + .sdram_wire_cas_n(DRAM_CAS_N), //.cas_n + .sdram_wire_cke(DRAM_CKE), //.cke + .sdram_wire_cs_n(DRAM_CS_N), //.cs_n + .sdram_wire_dq(DRAM_DQ), //.dq + .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm + .sdram_wire_ras_n(DRAM_RAS_N), //.ras_n + .sdram_wire_we_n(DRAM_WE_N) //.we_n +); ram main_memory( From 2a1f8df54e45930fb3dd05af6aa4059b94b1894b Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 13:37:34 -0500 Subject: [PATCH 3/9] Create SDRAM memory region --- sw/link.ld | 3 ++- sw/main.c | 16 +++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/sw/link.ld b/sw/link.ld index 489666d..66eb486 100644 --- a/sw/link.ld +++ b/sw/link.ld @@ -1,7 +1,8 @@ MEMORY { ZP: start = $0, size = $100, type = rw, define = yes; - RAM: start = $0200, size = $7D00, type = rw, define = yes; + RAM: start = $0200, size = $3D00, type = rw, define = yes; + SDRAM: start = $4000, size = $3ff00, type = rw, define = yes; ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O; } diff --git a/sw/main.c b/sw/main.c index 00fb9d4..ec6d2e2 100644 --- a/sw/main.c +++ b/sw/main.c @@ -5,16 +5,22 @@ #include "uart.h" int main() { - char s[16]; + uint8_t* test; + uint8_t i; + + test = (uint8_t*)0x5000; clrscr(); - cprintf("Hello, world!\n"); - while (1) { - cscanf("%15s", s); - cprintf("Read string: %s\n", s); + for (test = (uint8_t*)0x4000; test < (uint8_t*)0x5000; test++) { + for (i = 0; i < 64; i++) { + *test = i; + if (*test != i) + cprintf("Failed to read/write %x to %x\n", i, test); + } } + cprintf("Done! no SDRAM errors!\n"); return 0; } From 2d49fe22a708fdd33cc8cd12e2c302b5a14aa79c Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 13:53:07 -0500 Subject: [PATCH 4/9] ignore .sopcinfo This will be generated automatically when built. --- hw/fpga/.gitignore | 1 + hw/fpga/sdram_platform.sopcinfo | 4221 ------------------------------- 2 files changed, 1 insertion(+), 4221 deletions(-) delete mode 100644 hw/fpga/sdram_platform.sopcinfo diff --git a/hw/fpga/.gitignore b/hw/fpga/.gitignore index 52da622..405a13e 100644 --- a/hw/fpga/.gitignore +++ b/hw/fpga/.gitignore @@ -50,6 +50,7 @@ *.smsg *.sof *.sopc_builder +*.sopcinfo *.summary *.tcl *.txt # Explicitly add any text files used diff --git a/hw/fpga/sdram_platform.sopcinfo b/hw/fpga/sdram_platform.sopcinfo deleted file mode 100644 index 8591e4a..0000000 --- a/hw/fpga/sdram_platform.sopcinfo +++ /dev/null @@ -1,4221 +0,0 @@ - - - - - - - java.lang.Integer - 1647405925 - false - true - false - true - GENERATION_ID - - - java.lang.String - - false - true - false - true - UNIQUE_ID - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.String - 10M50DAF484C7G - false - true - false - true - DEVICE - - - java.lang.String - 7 - false - true - false - true - DEVICE_SPEEDGRADE - - - java.lang.Long - -1 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.Integer - -1 - false - true - false - true - CLOCK_DOMAIN - clk - - - java.lang.Integer - -1 - false - true - false - true - RESET_DOMAIN - clk - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - long - 0 - false - true - false - true - CLOCK_RATE - clk_in - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - qsys.ui.export_name - clk - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - in_clk - Input - 1 - clk - - - - - - qsys.ui.export_name - reset - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_in - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - clk_out - Output - 1 - clk - - - false - ext_bridge - clk - ext_bridge.clk - - - false - sdram_pll - inclk_interface - sdram_pll.inclk_interface - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - clk_in_reset - false - true - true - true - - - [Ljava.lang.String; - clk_in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - reset_n_out - Output - 1 - reset_n - - - - - - - int - 64 - false - true - true - true - - - java.lang.String - Mbytes - false - true - true - true - - - int - 8 - false - true - true - true - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.Long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 0 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - avalon_readdata - Input - 8 - readdata - - - avalon_waitrequest - Input - 1 - waitrequest - - - avalon_byteenable - Output - 1 - byteenable - - - avalon_read - Output - 1 - read - - - avalon_write - Output - 1 - write - - - avalon_writedata - Output - 8 - writedata - - - avalon_address - Output - 26 - address - - - false - sdram - s1 - sdram.s1 - 0 - 67108864 - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - address - Input - 26 - export - - - byte_enable - Input - 1 - export - - - read - Input - 1 - export - - - write - Input - 1 - export - - - write_data - Input - 8 - export - - - acknowledge - Output - 1 - export - - - read_data - Output - 8 - export - - - - - - - embeddedsw.CMacro.CAS_LATENCY - 3 - - - embeddedsw.CMacro.CONTENTS_INFO - - - - embeddedsw.CMacro.INIT_NOP_DELAY - 0.0 - - - embeddedsw.CMacro.INIT_REFRESH_COMMANDS - 2 - - - embeddedsw.CMacro.IS_INITIALIZED - 1 - - - embeddedsw.CMacro.POWERUP_DELAY - 200.0 - - - embeddedsw.CMacro.REFRESH_PERIOD - 15.625 - - - embeddedsw.CMacro.REGISTER_DATA_IN - 1 - - - embeddedsw.CMacro.SDRAM_ADDR_WIDTH - 25 - - - embeddedsw.CMacro.SDRAM_BANK_WIDTH - 2 - - - embeddedsw.CMacro.SDRAM_COL_WIDTH - 10 - - - embeddedsw.CMacro.SDRAM_DATA_WIDTH - 16 - - - embeddedsw.CMacro.SDRAM_NUM_BANKS - 4 - - - embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS - 1 - - - embeddedsw.CMacro.SDRAM_ROW_WIDTH - 13 - - - embeddedsw.CMacro.SHARED_DATA - 0 - - - embeddedsw.CMacro.SIM_MODEL_BASE - 0 - - - embeddedsw.CMacro.STARVATION_INDICATOR - 0 - - - embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE - "" - - - embeddedsw.CMacro.T_AC - 5.4 - - - embeddedsw.CMacro.T_MRD - 3 - - - embeddedsw.CMacro.T_RCD - 20.0 - - - embeddedsw.CMacro.T_RFC - 70.0 - - - embeddedsw.CMacro.T_RP - 20.0 - - - embeddedsw.CMacro.T_WR - 14.0 - - - embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR - SIM_DIR - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 1 - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 16 - - - double - 5.4 - false - true - true - true - - - double - 20.0 - false - true - true - true - - - double - 70.0 - false - true - true - true - - - double - 20.0 - false - true - true - true - - - double - 14.0 - false - true - true - true - - - int - 3 - false - true - true - true - - - int - 10 - false - true - true - true - - - int - 16 - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 2 - false - true - true - true - - - java.lang.String - single_Micron_MT48LC4M32B2_7_chip - false - true - false - true - - - int - 4 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - double - 200.0 - false - true - true - true - - - double - 15.625 - false - true - true - true - - - int - 13 - false - true - true - true - - - int - 0 - false - false - false - true - - - long - 3 - false - true - false - true - - - double - 0.0 - false - true - false - true - - - boolean - true - false - true - false - true - - - long - 50000000 - false - true - false - true - CLOCK_RATE - clk - - - java.lang.String - sdram_platform_sdram - false - true - false - true - UNIQUE_ID - - - long - 67108864 - true - true - false - true - - - int - 25 - true - true - false - true - - - int - 2 - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 67108864 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 7 - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - az_addr - Input - 25 - address - - - az_be_n - Input - 2 - byteenable_n - - - az_cs - Input - 1 - chipselect - - - az_data - Input - 16 - writedata - - - az_rd_n - Input - 1 - read_n - - - az_wr_n - Input - 1 - write_n - - - za_data - Output - 16 - readdata - - - za_valid - Output - 1 - readdatavalid - - - za_waitrequest - Output - 1 - waitrequest - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - zs_addr - Output - 13 - export - - - zs_ba - Output - 2 - export - - - zs_cas_n - Output - 1 - export - - - zs_cke - Output - 1 - export - - - zs_cs_n - Output - 1 - export - - - zs_dq - Bidir - 16 - export - - - zs_dqm - Output - 2 - export - - - zs_ras_n - Output - 1 - export - - - zs_we_n - Output - 1 - export - - - - - - - java.lang.String - altpll_avalon_elaboration - false - true - false - true - - - java.lang.String - altpll_avalon_post_edit - false - true - false - true - - - java.lang.String - MAX 10 - false - true - true - true - - - java.lang.String - 5 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 20000 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - NORMAL - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - CLK0 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - 1 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 0 - false - true - true - true - - - java.lang.String - -1000 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - 50 - false - true - true - true - - - java.lang.String - 50 - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_USED - false - true - true - true - - - java.lang.String - PORT_USED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_USED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - PORT_UNUSED - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - NO - false - true - true - true - - - java.lang.String - CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1000 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_UNUSED - false - true - false - true - - - java.lang.String - PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 0 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 -1.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 ns PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1647404711238322.mif PT#ACTIVECLK_CHECK 0 - false - true - false - true - - - java.lang.String - UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used - false - true - false - true - - - java.lang.String - IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 - false - true - false - true - - - java.lang.String - MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 - false - true - false - true - - - java.lang.String - IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} - false - true - false - true - - - java.lang.String - 0 - false - true - false - true - - - java.lang.String - MAX10FPGA - false - true - false - true - DEVICE_FAMILY - - - java.lang.Long - 50000000 - false - true - false - true - CLOCK_RATE - inclk_interface - - - java.lang.String - MAX 10 - false - true - false - true - DEVICE_FAMILY - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - inclk_interface - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - - - - embeddedsw.configuration.isMemoryDevice - false - - - embeddedsw.configuration.isNonVolatileStorage - false - - - embeddedsw.configuration.isPrintableDevice - false - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 16 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - inclk_interface - false - true - true - true - - - java.lang.String - inclk_interface_reset - false - true - true - true - - - int - 8 - false - true - true - true - - - java.math.BigInteger - - false - true - false - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - read - Input - 1 - read - - - write - Input - 1 - write - - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - writedata - Input - 32 - writedata - - - - - - java.lang.String - - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - c0 - Output - 1 - clk - - - false - sdram - clk - sdram.clk - - - - - - java.lang.String - - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - c1 - Output - 1 - clk - - - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - ext_bridge - avalon_master - sdram - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - sdram_pll - c0 - sdram - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - ext_bridge - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - sdram_pll - inclk_interface - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - sdram_pll - inclk_interface_reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - sdram - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - ext_bridge - reset - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Clock Source - 18.1 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 18.1 - - - 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 18.1 - - - 1 - altera_up_external_bus_to_avalon_bridge - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - External Bus to Avalon Bridge - 18.0 - - - 3 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 18.1 - - - 3 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 18.1 - - - 1 - avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 18.1 - - - 2 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 18.1 - - - 1 - altera_avalon_new_sdram_controller - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - SDRAM Controller Intel FPGA IP - 18.1 - - - 2 - avalon_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 18.1 - - - 1 - altpll - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - ALTPLL Intel FPGA IP - 18.1 - - - 2 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 18.1 - - - 1 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 18.1 - - - 3 - clock - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection - 18.1 - - - 3 - reset - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection - 18.1 - - 18.1 625 - - From ee97c4cbaa4b01e23fd6e86b074a09cd4cf9c8b9 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 14:25:26 -0500 Subject: [PATCH 5/9] Add platform generation to build stage --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4998610..16e5ba1 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -15,6 +15,7 @@ build-fpga: image: bslathi19/modelsim_18.1:lite script: - cd hw/fpga/ + - qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G - quartus_map super6502 -c super6502 test_addr_decode: From bbba99d09939f17ae1045668ed336822575b0327 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 15:05:25 -0500 Subject: [PATCH 6/9] Move data data segment to SDRAM --- sw/boot.s | 6 +++--- sw/link.ld | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/sw/boot.s b/sw/boot.s index 67e7b15..8cb6a79 100644 --- a/sw/boot.s +++ b/sw/boot.s @@ -8,7 +8,7 @@ .import _main .export __STARTUP__ : absolute = 1 ; Mark as startup -.import __RAM_START__, __RAM_SIZE__ ; Linker generated +.import __SDRAM_START__, __SDRAM_SIZE__ ; Linker generated .import copydata, zerobss, initlib, donelib @@ -29,9 +29,9 @@ _init: LDX #$FF ; Initialize stack pointer to $01FF ; --------------------------------------------------------------------------- ; Set cc65 argument stack pointer - LDA #<(__RAM_START__ + __RAM_SIZE__) + LDA #<(__SDRAM_START__ + __SDRAM_SIZE__) STA sp - LDA #>(__RAM_START__ + __RAM_SIZE__) + LDA #>(__SDRAM_START__ + __SDRAM_SIZE__) STA sp+1 ; --------------------------------------------------------------------------- diff --git a/sw/link.ld b/sw/link.ld index 66eb486..0d2897b 100644 --- a/sw/link.ld +++ b/sw/link.ld @@ -2,15 +2,15 @@ MEMORY { ZP: start = $0, size = $100, type = rw, define = yes; RAM: start = $0200, size = $3D00, type = rw, define = yes; - SDRAM: start = $4000, size = $3ff00, type = rw, define = yes; + SDRAM: start = $4000, size = $3ff0, type = rw, define = yes; ROM: start = $8000, size = $8000, fill = yes, fillval = $ff, file = %O; } SEGMENTS { ZEROPAGE: load = ZP, type = zp, define = yes; - DATA: load = ROM, type = rw, define = yes, run = RAM; - BSS: load = RAM, type = bss, define = yes; - HEAP: load = RAM, type = bss, optional = yes; + DATA: load = ROM, type = rw, define = yes, run = SDRAM; + BSS: load = SDRAM, type = bss, define = yes; + HEAP: load = SDRAM, type = bss, optional = yes; STARTUP: load = ROM, type = ro; ONCE: load = ROM, type = ro, optional = yes; CODE: load = ROM, type = ro; From 7619c7c54f8fbc846560cc180e1c8c726c851bae Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 15:05:37 -0500 Subject: [PATCH 7/9] new testing program --- sw/main.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/sw/main.c b/sw/main.c index ec6d2e2..b1830d0 100644 --- a/sw/main.c +++ b/sw/main.c @@ -5,22 +5,21 @@ #include "uart.h" int main() { - uint8_t* test; - uint8_t i; - - test = (uint8_t*)0x5000; + int i; + char s[16]; + s[15] = 0; clrscr(); + cprintf("Hello, world!\n"); - for (test = (uint8_t*)0x4000; test < (uint8_t*)0x5000; test++) { - for (i = 0; i < 64; i++) { - *test = i; - if (*test != i) - cprintf("Failed to read/write %x to %x\n", i, test); - } + while (1) { + cscanf("%15s", s); + cprintf("\n"); + for (i = 0; i < 16; i++) + cprintf("s[%d]=%c ", i, s[i]); + cprintf("\n"); + cprintf("Read string: %s\n", s); } - cprintf("Done! no SDRAM errors!\n"); - return 0; } From 7cb3183f85e10ed4232e6c9edc5fefcb522c53b5 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 17:12:43 -0500 Subject: [PATCH 8/9] Add sdram to address decode test --- hw/fpga/hvl/cs_testbench.sv | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv index d89ce93..e13a923 100644 --- a/hw/fpga/hvl/cs_testbench.sv +++ b/hw/fpga/hvl/cs_testbench.sv @@ -6,12 +6,13 @@ timeprecision 1ns; logic [15:0] addr; logic ram_cs; +logic sdram_cs; logic rom_cs; logic hex_cs; logic uart_cs; logic irq_cs; -int cs_count = ram_cs + rom_cs + hex_cs + uart_cs; +int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs; addr_decode dut(.*); @@ -23,11 +24,16 @@ initial begin : TEST_VECTORS assert(cs_count < 2) else $error("Multiple chip selects present!"); - if (i < 16'h7ff0) begin + if (i < 16'h4000) begin assert(ram_cs == '1) else $error("Bad CS! addr=%4x should have ram_cs!", addr); end + if (i >= 16'h4000 && i < 16'h7ff0) begin + assert(sdram_cs == '1) + else + $error("Bad CS! addr=%4x should have sdram_cs!", addr); + end if (i >= 16'h7ff0 && i < 16'h7ff4) begin assert(hex_cs == '1) else From 42a718408d809c98f2da4aee3449c322ac8b5a98 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 17 Mar 2022 17:49:20 -0500 Subject: [PATCH 9/9] Move SDRAM and state machine into its own file Cleans up the top level module a bit --- hw/fpga/sdram.sv | 87 ++++++++++++++++++++++++++++++++++++++++ hw/fpga/super6502.qsf | 1 + hw/fpga/super6502.sdc | 4 +- hw/fpga/super6502.sv | 93 +++++++++++++++---------------------------- 4 files changed, 122 insertions(+), 63 deletions(-) create mode 100644 hw/fpga/sdram.sv diff --git a/hw/fpga/sdram.sv b/hw/fpga/sdram.sv new file mode 100644 index 0000000..522596f --- /dev/null +++ b/hw/fpga/sdram.sv @@ -0,0 +1,87 @@ +module sdram( + input rst, + input clk_50, + input cpu_clk, + input [15:0] addr, + input sdram_cs, + input rwb, + input [7:0] data_in, + output [7:0] data_out, + + ///////// SDRAM ///////// + output wire DRAM_CLK, + output wire DRAM_CKE, + output wire [12: 0] DRAM_ADDR, + output wire [ 1: 0] DRAM_BA, + inout wire [15: 0] DRAM_DQ, + output wire DRAM_LDQM, + output wire DRAM_UDQM, + output wire DRAM_CS_N, + output wire DRAM_WE_N, + output wire DRAM_CAS_N, + output wire DRAM_RAS_N +); + +enum logic {ACCESS, WAIT } state, next_state; +logic ack; +logic _sdram_cs; + +always @(posedge clk_50) begin + if (rst) + state <= ACCESS; + else + state <= next_state; +end + +always_comb begin + next_state = state; + + case (state) + ACCESS: begin + if (sdram_cs & ~rwb & ack) + next_state = WAIT; + end + WAIT: begin + if (~cpu_clk) + next_state = ACCESS; + end + endcase +end + +always_comb begin + _sdram_cs = '0; + + case (state) + ACCESS: begin + _sdram_cs = sdram_cs & cpu_clk; + end + WAIT: begin + _sdram_cs = '0; + end + endcase +end + +sdram_platform u0 ( + .clk_clk (clk_50), // clk.clk + .reset_reset_n (1'b1), // reset.reset_n + .ext_bus_address (addr), // ext_bus.address + .ext_bus_byte_enable (1'b1), // .byte_enable + .ext_bus_read (_sdram_cs & rwb), // .read + .ext_bus_write (_sdram_cs & ~rwb), // .write + .ext_bus_write_data (data_in), // .write_data + .ext_bus_acknowledge (ack), // .acknowledge + .ext_bus_read_data (data_out), // .read_data + //SDRAM + .sdram_clk_clk(DRAM_CLK), //clk_sdram.clk + .sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr + .sdram_wire_ba(DRAM_BA), //.ba + .sdram_wire_cas_n(DRAM_CAS_N), //.cas_n + .sdram_wire_cke(DRAM_CKE), //.cke + .sdram_wire_cs_n(DRAM_CS_N), //.cs_n + .sdram_wire_dq(DRAM_DQ), //.dq + .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm + .sdram_wire_ras_n(DRAM_RAS_N), //.ras_n + .sdram_wire_we_n(DRAM_WE_N) //.we_n +); + +endmodule \ No newline at end of file diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf index 55f3a8e..e6fb6fa 100644 --- a/hw/fpga/super6502.qsf +++ b/hw/fpga/super6502.qsf @@ -350,6 +350,7 @@ set_location_assignment PIN_V22 -to DRAM_LDQM set_location_assignment PIN_U22 -to DRAM_RAS_N set_location_assignment PIN_J21 -to DRAM_UDQM set_location_assignment PIN_V20 -to DRAM_WE_N +set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv set_global_assignment -name QIP_FILE sdram_platform/synthesis/sdram_platform.qip set_global_assignment -name SYSTEMVERILOG_FILE uart.sv set_global_assignment -name SYSTEMVERILOG_FILE addr_decode.sv diff --git a/hw/fpga/super6502.sdc b/hw/fpga/super6502.sdc index b6b8652..a1b404a 100644 --- a/hw/fpga/super6502.sdc +++ b/hw/fpga/super6502.sdc @@ -3,7 +3,7 @@ #************************************************************** create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk_50}] -create_generated_clock -source [get_pins {u0|sdram_pll|sd1|pll7|clk[1] }] \ +create_generated_clock -source [get_pins {sdram|u0|sdram_pll|sd1|pll7|clk[1] }] \ -name clk_dram_ext [get_ports {DRAM_CLK}] derive_pll_clocks @@ -21,7 +21,7 @@ set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*] set_multicycle_path -from [get_clocks {clk_dram_ext}] \ - -to [get_clocks {u0|sdram_pll|sd1|pll7|clk[0] }] \ + -to [get_clocks {sdram|u0|sdram_pll|sd1|pll7|clk[0] }] \ -setup 2 set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}] diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv index 073a06d..8b6247d 100644 --- a/hw/fpga/super6502.sv +++ b/hw/fpga/super6502.sv @@ -26,18 +26,18 @@ module super6502( input logic UART_RXD, output logic UART_TXD, - ///////// SDRAM ///////// - output DRAM_CLK, - output DRAM_CKE, - output [12: 0] DRAM_ADDR, - output [ 1: 0] DRAM_BA, - inout [15: 0] DRAM_DQ, - output DRAM_LDQM, - output DRAM_UDQM, - output DRAM_CS_N, - output DRAM_WE_N, - output DRAM_CAS_N, - output DRAM_RAS_N + ///////// SDRAM ///////// + output DRAM_CLK, + output DRAM_CKE, + output [12: 0] DRAM_ADDR, + output [ 1: 0] DRAM_BA, + inout [15: 0] DRAM_DQ, + output DRAM_LDQM, + output DRAM_UDQM, + output DRAM_CS_N, + output DRAM_WE_N, + output DRAM_CAS_N, + output DRAM_RAS_N ); logic rst; @@ -107,60 +107,31 @@ always_comb begin cpu_data_out = 'x; end -enum logic {S_0, S_1 } teststate, next_teststate; -logic ack; -logic write; -logic _sdram_cs; -always @(posedge clk_50) begin - if (rst) - teststate <= S_0; - else - teststate <= next_teststate; -end +sdram sdram( + .rst(rst), + .clk_50(clk_50), + .cpu_clk(cpu_phi2), + .addr(cpu_addr), + .sdram_cs(sdram_cs), + .rwb(cpu_rwb), + .data_in(cpu_data_in), + .data_out(sdram_data_out), -always_comb begin - next_teststate = teststate; - write = '0; - _sdram_cs = '0; - case (teststate) - S_0: begin - write = sdram_cs & ~cpu_rwb & cpu_phi2; - _sdram_cs = sdram_cs & cpu_phi2; - if (sdram_cs & ~cpu_rwb & ack) - next_teststate = S_1; - end - S_1: begin - if (~(sdram_cs & ~cpu_rwb)) - next_teststate = S_0; - end - endcase -end - -sdram_platform u0 ( - .clk_clk (clk_50), // clk.clk - .reset_reset_n (1'b1), // reset.reset_n - .ext_bus_address (cpu_addr), // ext_bus.address - .ext_bus_byte_enable (1'b1), // .byte_enable - .ext_bus_read (_sdram_cs & cpu_rwb), // .read - .ext_bus_write (write), // .write - .ext_bus_write_data (cpu_data_in), // .write_data - .ext_bus_acknowledge (ack), // .acknowledge - .ext_bus_read_data (sdram_data_out), // .read_data //SDRAM - .sdram_clk_clk(DRAM_CLK), //clk_sdram.clk - .sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr - .sdram_wire_ba(DRAM_BA), //.ba - .sdram_wire_cas_n(DRAM_CAS_N), //.cas_n - .sdram_wire_cke(DRAM_CKE), //.cke - .sdram_wire_cs_n(DRAM_CS_N), //.cs_n - .sdram_wire_dq(DRAM_DQ), //.dq - .sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm - .sdram_wire_ras_n(DRAM_RAS_N), //.ras_n - .sdram_wire_we_n(DRAM_WE_N) //.we_n + .DRAM_CLK(DRAM_CLK), //clk_sdram.clk + .DRAM_ADDR(DRAM_ADDR), //sdram_wire.addr + .DRAM_BA(DRAM_BA), //.ba + .DRAM_CAS_N(DRAM_CAS_N), //.cas_n + .DRAM_CKE(DRAM_CKE), //.cke + .DRAM_CS_N(DRAM_CS_N), //.cs_n + .DRAM_DQ(DRAM_DQ), //.dq + .DRAM_UDQM(DRAM_UDQM), //.dqm + .DRAM_LDQM(DRAM_LDQM), + .DRAM_RAS_N(DRAM_RAS_N), //.ras_n + .DRAM_WE_N(DRAM_WE_N) //.we_n ); - ram main_memory( .address(cpu_addr[14:0]), .clock(clk),