diff --git a/.gitignore b/.gitignore index 5cd66f4..aa4d8c9 100644 --- a/.gitignore +++ b/.gitignore @@ -33,4 +33,5 @@ sim_build __pycache__ *.vcd *.fst.* -results.xml \ No newline at end of file +results.xml +html \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv b/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv index 4763f01..b7f74e5 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/network_processor.sv @@ -333,7 +333,6 @@ tcp #( .s_ip (proto_rx_ip[TCP_IDX]), .m_ip (proto_tx_ip[TCP_IDX]), - .m_dma_m2s_axi (m_dma_axil), // HACK - .m_dma_s2m_axi (dummy) + .m_dma_axil (m_dma_axil) ); endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh b/hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh index 92f82ed..60f2e88 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/run_precompile.sh @@ -1,4 +1,5 @@ -peakrdl regblock -t tcp_top_regfile tcp_stream_regs.rdl tcp_top_regs.rdl -o . --cpuif passthrough -peakrdl regblock -t tcp_stream_regs tcp_stream_regs.rdl -o . --cpuif passthrough +peakrdl regblock -t tcp_top_regfile ../../../stream_dmas/src/regs/m2s_dma_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl -o . --cpuif passthrough +peakrdl regblock -t tcp_stream_regs ../../../stream_dmas/src/regs/m2s_dma_regs.rdl tcp_stream_regs.rdl -o . --cpuif passthrough peakrdl regblock -t mac_regs mac_regs.rdl -o . --cpuif passthrough -peakrdl regblock -t ntw_top_regfile mac_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl ntw_top_regs.rdl -o . --cpuif axi4-lite-flat \ No newline at end of file +peakrdl regblock -t ntw_top_regfile mac_regs.rdl ../../../stream_dmas/src/regs/m2s_dma_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl ntw_top_regs.rdl -o . --cpuif axi4-lite-flat +peakrdl html -t ntw_top_regfile mac_regs.rdl ../../../stream_dmas/src/regs/m2s_dma_regs.rdl tcp_stream_regs.rdl tcp_top_regs.rdl ntw_top_regs.rdl -o html diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.rdl b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.rdl index 31ab8b2..df22881 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.rdl +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.rdl @@ -132,4 +132,6 @@ addrmap tcp_stream_regs { } rx_bad_crc @ 0x8; }; + + external m2s_dma_regs m2s_dma_regs @ 0x20; }; \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.sv b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.sv index 7ab91f5..4c8238a 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs.sv @@ -7,7 +7,7 @@ module tcp_stream_regs ( input wire s_cpuif_req, input wire s_cpuif_req_is_wr, - input wire [4:0] s_cpuif_addr, + input wire [5:0] s_cpuif_addr, input wire [31:0] s_cpuif_wr_data, input wire [31:0] s_cpuif_wr_biten, output wire s_cpuif_req_stall_wr, @@ -27,7 +27,7 @@ module tcp_stream_regs ( //-------------------------------------------------------------------------- logic cpuif_req; logic cpuif_req_is_wr; - logic [4:0] cpuif_addr; + logic [5:0] cpuif_addr; logic [31:0] cpuif_wr_data; logic [31:0] cpuif_wr_biten; logic cpuif_req_stall_wr; @@ -54,10 +54,27 @@ module tcp_stream_regs ( assign s_cpuif_wr_err = cpuif_wr_err; logic cpuif_req_masked; + logic external_req; + logic external_pending; + logic external_wr_ack; + logic external_rd_ack; + always_ff @(posedge clk) begin + if(rst) begin + external_pending <= '0; + end else begin + if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1; + else if(external_wr_ack | external_rd_ack) external_pending <= '0; + assert(!external_wr_ack || (external_pending | external_req)) + else $error("An external wr_ack strobe was asserted when no external request was active"); + assert(!external_rd_ack || (external_pending | external_req)) + else $error("An external rd_ack strobe was asserted when no external request was active"); + end + end // Read & write latencies are balanced. Stalls not required - assign cpuif_req_stall_rd = '0; - assign cpuif_req_stall_wr = '0; + // except if external + assign cpuif_req_stall_rd = external_pending; + assign cpuif_req_stall_wr = external_pending; assign cpuif_req_masked = cpuif_req & !(!cpuif_req_is_wr & cpuif_req_stall_rd) & !(cpuif_req_is_wr & cpuif_req_stall_wr); @@ -71,22 +88,35 @@ module tcp_stream_regs ( logic dest_port; logic dest_ip; logic control; + logic m2s_dma_regs; } decoded_reg_strb_t; decoded_reg_strb_t decoded_reg_strb; + logic decoded_strb_is_external; + + logic [5:0] decoded_addr; + logic decoded_req; logic decoded_req_is_wr; logic [31:0] decoded_wr_data; logic [31:0] decoded_wr_biten; always_comb begin - decoded_reg_strb.source_port = cpuif_req_masked & (cpuif_addr == 5'h0); - decoded_reg_strb.source_ip = cpuif_req_masked & (cpuif_addr == 5'h4); - decoded_reg_strb.dest_port = cpuif_req_masked & (cpuif_addr == 5'h8); - decoded_reg_strb.dest_ip = cpuif_req_masked & (cpuif_addr == 5'hc); - decoded_reg_strb.control = cpuif_req_masked & (cpuif_addr == 5'h10); + automatic logic is_external; + is_external = '0; + decoded_reg_strb.source_port = cpuif_req_masked & (cpuif_addr == 6'h0); + decoded_reg_strb.source_ip = cpuif_req_masked & (cpuif_addr == 6'h4); + decoded_reg_strb.dest_port = cpuif_req_masked & (cpuif_addr == 6'h8); + decoded_reg_strb.dest_ip = cpuif_req_masked & (cpuif_addr == 6'hc); + decoded_reg_strb.control = cpuif_req_masked & (cpuif_addr == 6'h10); + decoded_reg_strb.m2s_dma_regs = cpuif_req_masked & (cpuif_addr >= 6'h20) & (cpuif_addr <= 6'h20 + 6'hf); + is_external |= cpuif_req_masked & (cpuif_addr >= 6'h20) & (cpuif_addr <= 6'h20 + 6'hf); + decoded_strb_is_external = is_external; + external_req = is_external; end // Pass down signals to next stage + assign decoded_addr = cpuif_addr; + assign decoded_req = cpuif_req_masked; assign decoded_req_is_wr = cpuif_req_is_wr; assign decoded_wr_data = cpuif_wr_data; @@ -325,24 +355,46 @@ module tcp_stream_regs ( end end assign hwif_out.control.close.value = field_storage.control.close.value; + assign hwif_out.m2s_dma_regs.req = decoded_reg_strb.m2s_dma_regs; + assign hwif_out.m2s_dma_regs.addr = decoded_addr[4:0]; + assign hwif_out.m2s_dma_regs.req_is_wr = decoded_req_is_wr; + assign hwif_out.m2s_dma_regs.wr_data = decoded_wr_data; + assign hwif_out.m2s_dma_regs.wr_biten = decoded_wr_biten; //-------------------------------------------------------------------------- // Write response //-------------------------------------------------------------------------- - assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + always_comb begin + automatic logic wr_ack; + wr_ack = '0; + wr_ack |= hwif_in.m2s_dma_regs.wr_ack; + external_wr_ack = wr_ack; + end + assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_strb_is_external); // Writes are always granted with no error response assign cpuif_wr_err = '0; //-------------------------------------------------------------------------- // Readback //-------------------------------------------------------------------------- + logic readback_external_rd_ack_c; + always_comb begin + automatic logic rd_ack; + rd_ack = '0; + rd_ack |= hwif_in.m2s_dma_regs.rd_ack; + readback_external_rd_ack_c = rd_ack; + end + + logic readback_external_rd_ack; + + assign readback_external_rd_ack = readback_external_rd_ack_c; logic readback_err; logic readback_done; logic [31:0] readback_data; // Assign readback values to a flattened array - logic [31:0] readback_array[5]; + logic [31:0] readback_array[6]; assign readback_array[0][31:0] = (decoded_reg_strb.source_port && !decoded_req_is_wr) ? field_storage.source_port.d.value : '0; assign readback_array[1][31:0] = (decoded_reg_strb.source_ip && !decoded_req_is_wr) ? field_storage.source_ip.d.value : '0; assign readback_array[2][31:0] = (decoded_reg_strb.dest_port && !decoded_req_is_wr) ? field_storage.dest_port.d.value : '0; @@ -352,18 +404,20 @@ module tcp_stream_regs ( assign readback_array[4][2:2] = (decoded_reg_strb.control && !decoded_req_is_wr) ? field_storage.control.close.value : '0; assign readback_array[4][5:3] = (decoded_reg_strb.control && !decoded_req_is_wr) ? hwif_in.control.state.next : '0; assign readback_array[4][31:6] = '0; + assign readback_array[5] = hwif_in.m2s_dma_regs.rd_ack ? hwif_in.m2s_dma_regs.rd_data : '0; // Reduce the array always_comb begin automatic logic [31:0] readback_data_var; - readback_done = decoded_req & ~decoded_req_is_wr; + readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external; readback_err = '0; readback_data_var = '0; - for(int i=0; i<5; i++) readback_data_var |= readback_array[i]; + for(int i=0; i<6; i++) readback_data_var |= readback_array[i]; readback_data = readback_data_var; end - assign cpuif_rd_ack = readback_done; + assign external_rd_ack = readback_external_rd_ack; + assign cpuif_rd_ack = readback_done | readback_external_rd_ack; assign cpuif_rd_data = readback_data; assign cpuif_rd_err = readback_err; endmodule diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs_pkg.sv b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs_pkg.sv index f053abf..f385fc4 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs_pkg.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_stream_regs_pkg.sv @@ -4,7 +4,7 @@ package tcp_stream_regs_pkg; localparam TCP_STREAM_REGS_DATA_WIDTH = 32; - localparam TCP_STREAM_REGS_MIN_ADDR_WIDTH = 5; + localparam TCP_STREAM_REGS_MIN_ADDR_WIDTH = 6; typedef struct { logic hwclr; @@ -24,8 +24,15 @@ package tcp_stream_regs_pkg; tcp_stream_regs__control__state__in_t state; } tcp_stream_regs__control__in_t; + typedef struct { + logic rd_ack; + logic [31:0] rd_data; + logic wr_ack; + } m2s_dma_regs__external__in_t; + typedef struct { tcp_stream_regs__control__in_t control; + m2s_dma_regs__external__in_t m2s_dma_regs; } tcp_stream_regs__in_t; typedef struct { @@ -78,11 +85,20 @@ package tcp_stream_regs_pkg; tcp_stream_regs__control__close__out_t close; } tcp_stream_regs__control__out_t; + typedef struct { + logic req; + logic [3:0] addr; + logic req_is_wr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + } m2s_dma_regs__external__out_t; + typedef struct { tcp_stream_regs__source_port__out_t source_port; tcp_stream_regs__source_ip__out_t source_ip; tcp_stream_regs__dest_port__out_t dest_port; tcp_stream_regs__dest_ip__out_t dest_ip; tcp_stream_regs__control__out_t control; + m2s_dma_regs__external__out_t m2s_dma_regs; } tcp_stream_regs__out_t; endpackage diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv index 0c3bfe9..7134e46 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile.sv @@ -99,8 +99,8 @@ module tcp_top_regfile ( automatic logic is_external; is_external = '0; for(int i0=0; i0<8; i0++) begin - decoded_reg_strb.tcp_streams[i0] = cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h13); - is_external |= cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h13); + decoded_reg_strb.tcp_streams[i0] = cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h2f); + is_external |= cpuif_req_masked & (cpuif_addr >= 9'h0 + i0*9'h40) & (cpuif_addr <= 9'h0 + i0*9'h40 + 9'h2f); end decoded_strb_is_external = is_external; external_req = is_external; @@ -123,7 +123,7 @@ module tcp_top_regfile ( for(genvar i0=0; i0<8; i0++) begin assign hwif_out.tcp_streams[i0].req = decoded_reg_strb.tcp_streams[i0]; - assign hwif_out.tcp_streams[i0].addr = decoded_addr[4:0]; + assign hwif_out.tcp_streams[i0].addr = decoded_addr[5:0]; assign hwif_out.tcp_streams[i0].req_is_wr = decoded_req_is_wr; assign hwif_out.tcp_streams[i0].wr_data = decoded_wr_data; assign hwif_out.tcp_streams[i0].wr_biten = decoded_wr_biten; diff --git a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv index 9631184..e8699fb 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/regs/tcp_top_regfile_pkg.sv @@ -18,7 +18,7 @@ package tcp_top_regfile_pkg; typedef struct { logic req; - logic [4:0] addr; + logic [5:0] addr; logic req_is_wr; logic [31:0] wr_data; logic [31:0] wr_biten; diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv index 6a997ef..3d0ca7f 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv @@ -31,9 +31,7 @@ module tcp #( /* * AXI DMA Interface */ - axil_intf.MASTER m_dma_m2s_axi, - axil_intf.MASTER m_dma_s2m_axi - + axil_intf.MASTER m_dma_axil ); tcp_top_regfile_pkg::tcp_top_regfile__in_t tcp_hwif_in; @@ -88,8 +86,17 @@ wire [NUM_TCP-1:0] xbar_s_m2s_axi_rready; wire [NUM_TCP*32-1:0] xbar_s_m2s_axi_rdata; wire [NUM_TCP*2-1:0] xbar_s_m2s_axi_rresp; +wire [NUM_TCP-1:0] xbar_s_s2m_axi_arvalid; +wire [NUM_TCP-1:0] xbar_s_s2m_axi_arready; +wire [NUM_TCP*32-1:0] xbar_s_s2m_axi_araddr; +wire [NUM_TCP*3-1:0] xbar_s_s2m_axi_arprot; +wire [NUM_TCP-1:0] xbar_s_s2m_axi_rvalid; +wire [NUM_TCP-1:0] xbar_s_s2m_axi_rready; +wire [NUM_TCP*32-1:0] xbar_s_s2m_axi_rdata; +wire [NUM_TCP*2-1:0] xbar_s_s2m_axi_rresp; + axilxbar #( - .NM(NUM_TCP), + .NM(NUM_TCP*2), .NS(1), .SLAVE_ADDR( {32'h0, 32'hffffffff} // full address space @@ -111,14 +118,14 @@ axilxbar #( .S_AXI_BREADY ('0), .S_AXI_BRESP (), - .S_AXI_ARVALID (xbar_s_m2s_axi_arvalid), - .S_AXI_ARREADY (xbar_s_m2s_axi_arready), - .S_AXI_ARADDR (xbar_s_m2s_axi_araddr), - .S_AXI_ARPROT (xbar_s_m2s_axi_arprot), - .S_AXI_RVALID (xbar_s_m2s_axi_rvalid), - .S_AXI_RREADY (xbar_s_m2s_axi_rready), - .S_AXI_RDATA (xbar_s_m2s_axi_rdata), - .S_AXI_RRESP (xbar_s_m2s_axi_rresp), + .S_AXI_ARVALID ({xbar_s_m2s_axi_arvalid, xbar_s_s2m_axi_arvalid }), + .S_AXI_ARREADY ({xbar_s_m2s_axi_arready, xbar_s_s2m_axi_arready }), + .S_AXI_ARADDR ({xbar_s_m2s_axi_araddr, xbar_s_s2m_axi_araddr }), + .S_AXI_ARPROT ({xbar_s_m2s_axi_arprot, xbar_s_s2m_axi_arprot }), + .S_AXI_RVALID ({xbar_s_m2s_axi_rvalid, xbar_s_s2m_axi_rvalid }), + .S_AXI_RREADY ({xbar_s_m2s_axi_rready, xbar_s_s2m_axi_rready }), + .S_AXI_RDATA ({xbar_s_m2s_axi_rdata, xbar_s_s2m_axi_rdata }), + .S_AXI_RRESP ({xbar_s_m2s_axi_rresp, xbar_s_s2m_axi_rresp }), .M_AXI_AWADDR (), .M_AXI_AWPROT (), @@ -132,30 +139,18 @@ axilxbar #( .M_AXI_BVALID ('0), .M_AXI_BREADY (), - .M_AXI_ARADDR (m_dma_s2m_axi.araddr), - .M_AXI_ARPROT (m_dma_s2m_axi.arprot), - .M_AXI_ARVALID (m_dma_s2m_axi.arvalid), - .M_AXI_ARREADY (m_dma_s2m_axi.arready), - .M_AXI_RDATA (m_dma_s2m_axi.rdata), - .M_AXI_RRESP (m_dma_s2m_axi.rresp), - .M_AXI_RVALID (m_dma_s2m_axi.rvalid), - .M_AXI_RREADY (m_dma_s2m_axi.rready) + .M_AXI_ARADDR (m_dma_axil.araddr), + .M_AXI_ARPROT (m_dma_axil.arprot), + .M_AXI_ARVALID (m_dma_axil.arvalid), + .M_AXI_ARREADY (m_dma_axil.arready), + .M_AXI_RDATA (m_dma_axil.rdata), + .M_AXI_RRESP (m_dma_axil.rresp), + .M_AXI_RVALID (m_dma_axil.rvalid), + .M_AXI_RREADY (m_dma_axil.rready) ); generate for (genvar i = 0; i < NUM_TCP; i++) begin - logic req; - logic req_is_wr; - logic [5:0] addr; - logic [31:0] wr_data; - logic [31:0] wr_biten; - - assign req = tcp_hwif_out.tcp_streams[i].req; - assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr; - assign addr = tcp_hwif_out.tcp_streams[i].addr; - assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data; - assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten; - assign xbar_s_m2s_axi_arvalid[i] = m2s_stream_axil[i].arvalid; assign m2s_stream_axil[i].arready = xbar_s_m2s_axi_arready[i]; assign xbar_s_m2s_axi_araddr[32*i+:32] = m2s_stream_axil[i].araddr; @@ -165,28 +160,14 @@ generate assign m2s_stream_axil[i].rdata = xbar_s_m2s_axi_rdata[32*i+:32]; assign m2s_stream_axil[i].rresp = xbar_s_m2s_axi_rresp[2*i+:2]; - m2s_dma #( - .AXIS_DATA_WIDTH(8) - ) u_m2s_dma ( - .i_clk (i_clk), - .i_rst (i_rst), - - .s_cpuif_req (req), - .s_cpuif_req_is_wr (req_is_wr), - .s_cpuif_addr (addr), - .s_cpuif_wr_data (wr_data), - .s_cpuif_wr_biten (wr_biten), - .s_cpuif_req_stall_wr (), - .s_cpuif_req_stall_rd (), - .s_cpuif_rd_ack (tcp_hwif_in.tcp_streams[i].rd_ack), - .s_cpuif_rd_err (), - .s_cpuif_rd_data (tcp_hwif_in.tcp_streams[i].rd_data), - .s_cpuif_wr_ack (tcp_hwif_in.tcp_streams[i].wr_ack), - .s_cpuif_wr_err (), - - .m_axil (m2s_stream_axil[i]), - .m_axis (tcp_stream_rx_axis[i]) - ); + assign xbar_s_s2m_axi_arvalid[i] = s2m_stream_axil[i].arvalid; + assign s2m_stream_axil[i].arready = xbar_s_s2m_axi_arready[i]; + assign xbar_s_s2m_axi_araddr[32*i+:32] = s2m_stream_axil[i].araddr; + assign xbar_s_s2m_axi_arprot[3*i+:3] = s2m_stream_axil[i].arprot; + assign s2m_stream_axil[i].rvalid = xbar_s_s2m_axi_rvalid[i]; + assign xbar_s_s2m_axi_rready[i] = s2m_stream_axil[i].rready; + assign s2m_stream_axil[i].rdata = xbar_s_s2m_axi_rdata[32*i+:32]; + assign s2m_stream_axil[i].rresp = xbar_s_s2m_axi_rresp[2*i+:2]; end endgenerate @@ -213,18 +194,6 @@ ip_arb_mux_wrapper #( generate for (genvar i = 0; i < NUM_TCP; i++) begin - logic req; - logic req_is_wr; - logic [5:0] addr; - logic [31:0] wr_data; - logic [31:0] wr_biten; - - assign req = tcp_hwif_out.tcp_streams[i].req; - assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr; - assign addr = tcp_hwif_out.tcp_streams[i].addr; - assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data; - assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten; - tcp_stream u_tcp_stream ( .clk (i_clk), .rst (i_rst), @@ -244,7 +213,10 @@ generate .s_cpuif_wr_err (), .s_ip_rx (tcp_stream_rx_ip[i]), - .m_ip_tx (tcp_stream_tx_ip[i]) + .m_ip_tx (tcp_stream_tx_ip[i]), + + .m_m2s_axil (m2s_stream_axil[i]), + .m_s2m_axil (s2m_stream_axil[i]) ); end endgenerate diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv index 1568579..bb8614c 100644 --- a/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv +++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv @@ -21,9 +21,14 @@ module tcp_stream #( output wire s_cpuif_wr_err, ip_intf.SLAVE s_ip_rx, - ip_intf.MASTER m_ip_tx + ip_intf.MASTER m_ip_tx, + + axil_intf.MASTER m_m2s_axil, + axil_intf.MASTER m_s2m_axil ); +axis_intf m2s_axis(); +axis_intf s2m_axis(); // regs tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in; @@ -51,6 +56,29 @@ tcp_stream_regs u_tcp_stream_regs ( .hwif_out (hwif_out) ); +m2s_dma #( + .AXIS_DATA_WIDTH(DATA_WIDTH) +) u_m2s_dma ( + .i_clk (i_clk), + .i_rst (i_rst), + + .s_cpuif_req (hwif_out.m2s_dma_regs.req), + .s_cpuif_req_is_wr (hwif_out.m2s_dma_regs.req_is_wr), + .s_cpuif_addr (hwif_out.m2s_dma_regs.addr), + .s_cpuif_wr_data (hwif_out.m2s_dma_regs.wr_data), + .s_cpuif_wr_biten (hwif_out.m2s_dma_regs.wr_biten), + .s_cpuif_req_stall_wr (), + .s_cpuif_req_stall_rd (), + .s_cpuif_rd_ack (hwif_in.m2s_dma_regs.rd_ack), + .s_cpuif_rd_err (), + .s_cpuif_rd_data (hwif_in.m2s_dma_regs.rd_data), + .s_cpuif_wr_ack (hwif_in.m2s_dma_regs.wr_ack), + .s_cpuif_wr_err (), + + .m_axil (m_m2s_axil), + .m_axis (m2s_axis) +); + // tcp state manager // tx buffer