From 673386f9f914aab45ddb1aaf501e42c27c5f0b88 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 12 Oct 2023 19:32:12 -0700
Subject: [PATCH] Change clk_2 to clk_cpu

---
 hw/efinix_fpga/simulation/src/sim_top.sv | 14 +++++++-------
 hw/efinix_fpga/src/super6502.sv          | 24 ++++++++++++------------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 4d18031..474af69 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -4,7 +4,7 @@ module sim_top();
 
 `include "include/super6502_sdram_controller_define.vh"
 
-logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
+logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
 
 // clk_100
 initial begin
@@ -30,11 +30,11 @@ initial begin
     end
 end
 
-// clk_2
+// clk_cpu
 initial begin
-    r_clk_2 <= '1;
+    r_clk_cpu <= '1;
     forever begin
-        #250 r_clk_2 <= ~r_clk_2;
+        #250 r_clk_cpu <= ~r_clk_cpu;
     end
 end
 
@@ -47,9 +47,9 @@ logic button_reset;
 
 initial begin
     button_reset <= '0;
-    repeat(10) @(r_clk_2);
+    repeat(10) @(r_clk_cpu);
     button_reset <= '1;
-    repeat(1000000) @(r_clk_2);
+    repeat(1000000) @(r_clk_cpu);
     $finish();
 end
 
@@ -101,7 +101,7 @@ super6502 u_dut(
     .i_sdrclk(r_sdrclk),
     .i_tACclk(~r_sdrclk),
     .clk_50(r_clk_50),
-    .clk_2(r_clk_2),
+    .clk_cpu(r_clk_cpu),
     .button_reset(button_reset),
     .cpu_resb(w_cpu_reset),
     .cpu_addr(w_cpu_addr),
diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv
index b0b1a49..5cdc894 100644
--- a/hw/efinix_fpga/src/super6502.sv
+++ b/hw/efinix_fpga/src/super6502.sv
@@ -11,7 +11,7 @@ module super6502
     input button_reset,
     input pll_cpu_locked,
     input clk_50,
-    input clk_2,
+    input clk_cpu,
     input logic [15:0] cpu_addr,
     output logic [7:0] cpu_data_out,
     output logic [7:0] cpu_data_oe,
@@ -56,11 +56,11 @@ assign cpu_nmib = '1;
 logic w_wait;
 assign cpu_rdy = ~w_wait;
 
-assign cpu_phi2 = clk_2;
+assign cpu_phi2 = clk_cpu;
 
 logic w_sdr_init_done;
 
-always @(posedge clk_2) begin
+always @(posedge clk_cpu) begin
     if (button_reset == '0) begin
         cpu_resb <= '0;
     end 
@@ -124,12 +124,12 @@ end
 
 rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
     .addr(cpu_addr[11:0]),
-    .clk(clk_2),
+    .clk(clk_cpu),
     .data(w_rom_data_out)
 );
 
 leds u_leds(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .i_data(cpu_data_in),
     .o_data(w_leds_data_out),
     .cs(w_leds_cs),
@@ -140,7 +140,7 @@ leds u_leds(
 logic w_timer_irqb;
 
 timer u_timer(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
     .o_data(w_timer_data_out),
@@ -151,7 +151,7 @@ timer u_timer(
 );
 
 multiplier u_multiplier(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
     .o_data(w_multiplier_data_out),
@@ -161,7 +161,7 @@ multiplier u_multiplier(
 );
 
 divider_wrapper u_divider(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .divclk(clk_50),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
@@ -174,7 +174,7 @@ divider_wrapper u_divider(
 logic w_uart_irqb;
 
 uart_wrapper u_uart(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .clk_50(clk_50),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
@@ -188,7 +188,7 @@ uart_wrapper u_uart(
 );
 
 spi_controller spi_controller(
-    .i_clk(clk_2),
+    .i_clk(clk_cpu),
     .i_rst(~cpu_resb),
     .i_cs(w_spi_cs),
     .i_rwb(cpu_rwb),
@@ -204,7 +204,7 @@ spi_controller spi_controller(
 
 
 sdram_adapter u_sdram_adapter(
-    .i_cpuclk(clk_2),
+    .i_cpuclk(clk_cpu),
     .i_arst(~button_reset),
     .i_sysclk(i_sysclk),
     .i_sdrclk(i_sdrclk),
@@ -234,7 +234,7 @@ sdram_adapter u_sdram_adapter(
 );
 
 interrupt_controller u_interrupt_controller(
-    .clk(clk_2),
+    .clk(clk_cpu),
     .reset(~cpu_resb),
     .i_data(cpu_data_in),
     .o_data(w_irq_data_out),