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Change clk_2 to clk_cpu

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This commit is contained in:
Byron Lathi
2023-10-12 19:32:12 -07:00
parent 893a0f1a9e
commit 673386f9f9
2 changed files with 19 additions and 19 deletions
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14
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -4,7 +4,7 @@ module sim_top();
`include "include/super6502_sdram_controller_define.vh"
logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
// clk_100
initial begin
@@ -30,11 +30,11 @@ initial begin
end
end
// clk_2
// clk_cpu
initial begin
r_clk_2 <= '1;
r_clk_cpu <= '1;
forever begin
#250 r_clk_2 <= ~r_clk_2;
#250 r_clk_cpu <= ~r_clk_cpu;
end
end
@@ -47,9 +47,9 @@ logic button_reset;
initial begin
button_reset <= '0;
repeat(10) @(r_clk_2);
repeat(10) @(r_clk_cpu);
button_reset <= '1;
repeat(1000000) @(r_clk_2);
repeat(1000000) @(r_clk_cpu);
$finish();
end
@@ -101,7 +101,7 @@ super6502 u_dut(
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_2(r_clk_2),
.clk_cpu(r_clk_cpu),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),