From 68fe3d1851bc0f0376132513a6d7dd4d2004a2e0 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 21 Sep 2024 19:21:31 -0700
Subject: [PATCH] Add ntw sim to ci

---
 .gitlab-ci.yml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e77ed88..92d0221 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -25,3 +25,18 @@ sim:
     - source init_env.sh
     - make sim
 
+ntw_sim:
+  stage: sim
+  needs: []
+  tags:
+    - linux
+  script:
+    - source init_env.sh
+    - cd hw/super6502_fpga/src/sub/network_processor/sim/cocotb
+    - make -j `nproc`
+  artifacts:
+    when: always
+    paths:
+      - hw/super6502_fpga/src/sub/network_processor/sim/cocotb/results.xml
+    reports:
+      junit: hw/super6502_fpga/src/sub/network_processor/sim/cocotb/results.xml
\ No newline at end of file