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Implement basic SPI controller

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This commit is contained in:
Byron Lathi
2023-07-21 23:01:37 -07:00
parent 85f12c75f1
commit 6a1a76db35
4 changed files with 501 additions and 7 deletions
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25
hw/efinix_fpga/spi_controller.sv
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@@ -28,18 +28,25 @@ logic [7:0] r_control;
logic [8:0] r_clock_counter;
logic active;
logic [2:0] count;
logic spi_clk;
logic r_spi_mosi;
always @(posedge i_clk) begin
assign o_spi_cs = ~r_control[0];
assign o_spi_clk = spi_clk;
assign o_spi_mosi = r_spi_mosi;
always @(negedge i_clk) begin
if (i_rst) begin
r_baud_rate <= 8'h10;
r_baud_rate <= 8'h1;
r_input_data <= '0;
r_output_data <= '0;
r_control <= '0;
r_clock_counter <= '0;
count <= '0;
spi_clk <= '0;
active <= '0;
end else begin
if (~i_rwb & i_cs) begin
unique case (i_addr)
@@ -54,16 +61,22 @@ always @(posedge i_clk) begin
end
if (active) begin
r_spi_mosi <= r_output_data[0];
r_spi_mosi <= r_output_data[7];
r_clock_counter <= r_clock_counter + 9'b1;
if (r_clock_counter >= r_baud_rate) begin
r_clock_counter <= '0;
spi_clk <= ~spi_clk;
// rising edge
if (spi_clk == '0) begin
r_output_data <= r_output_data >> 1;
r_output_data <= r_output_data << 1;
count <= count + 1;
end
// falling edge
if (spi_clk == '1) begin
r_input_data <= {r_input_data[7:1], i_spi_miso};
r_input_data <= {r_input_data[6:0], i_spi_miso};
if (count == '0) begin
active <= '0;
end
end
end
@@ -76,7 +89,7 @@ always_comb begin
0: o_data = r_baud_rate;
1: o_data = r_input_data;
2:;
3: o_data = r_control;
3: o_data = {active, r_control[6:0]};
endcase
end