From 6b7f7837dd1712a45f0d835d9dba4cea5add7f14 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 17 Jul 2024 00:17:24 -0700 Subject: [PATCH] Use ZipCPU SD controller I trust it more than the other one --- .gitmodules | 9 +- hw/super6502_fpga/sources.list | 5 - hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 225 ++++++++++-------- hw/super6502_fpga/src/sub/axi_crossbar | 1 - .../sdcard_controller_wrapper.sv | 215 ----------------- .../sdcard_mass_storage_controller | 1 - hw/super6502_fpga/src/sub/sdspi | 1 + hw/super6502_fpga/super6502_fpga.xml | 194 +++++++-------- 8 files changed, 227 insertions(+), 424 deletions(-) delete mode 160000 hw/super6502_fpga/src/sub/axi_crossbar delete mode 100644 hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv delete mode 160000 hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller create mode 160000 hw/super6502_fpga/src/sub/sdspi diff --git a/.gitmodules b/.gitmodules index daf53d6..23a14c6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,6 @@ [submodule "hw/super6502_fpga/src/sub/rtl-common"] path = hw/super6502_fpga/src/sub/rtl-common url = ../rtl-common.git -[submodule "hw/super6502_fpga/src/sub/axi_crossbar"] - path = hw/super6502_fpga/src/sub/axi_crossbar - url = ../axi_crossbar.git [submodule "sw/toolchain/cc65"] path = sw/toolchain/cc65 url = ../cc65.git @@ -16,6 +13,6 @@ [submodule "hw/super6502_fpga/src/sub/wb2axip"] path = hw/super6502_fpga/src/sub/wb2axip url = ../wb2axip.git -[submodule "hw/super6502_fpga/src/sub/sdcard_mass_storage_controller"] - path = hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller - url = ../sdcard_mass_storage_controller.git +[submodule "hw/super6502_fpga/src/sub/sdspi"] + path = hw/super6502_fpga/src/sub/sdspi + url = git@git.byronlathi.com:bslathi19/sdspi.git diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list index 59e3c2a..f4c54e9 100644 --- a/hw/super6502_fpga/sources.list +++ b/hw/super6502_fpga/sources.list @@ -1,9 +1,4 @@ src/rtl/super_6502_fpga.sv -src/sub/axi_crossbar/src/rtl/axi_crossbar.sv -src/sub/axi_crossbar/src/rtl/axi_master.sv -src/sub/axi_crossbar/src/rtl/axi_slave.sv -src/sub/axi_crossbar/src/rtl/rr_scheduler.sv -src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv src/sub/cpu_wrapper/cpu_wrapper.sv src/sub/rtl-common/src/rtl/async_fifo.sv src/sub/rtl-common/src/rtl/axi4_lite_ram.sv diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 0e4b29a..6d4b0f1 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -43,8 +43,8 @@ module super6502_fpga( input i_sd_dat, output o_sd_dat, output o_sd_dat_oe, - output o_sd_clk, - output o_sd_cs + output o_sd_clk + // input i_sd_cd ); @@ -153,23 +153,23 @@ logic [1:0] sdram_RRESP; // These are for the control/status registers -logic sd_controller_csr_AWVALID; -logic sd_controller_csr_AWREADY; -logic [ADDR_WIDTH-1:0] sd_controller_csr_AWADDR; -logic sd_controller_csr_WVALID; -logic sd_controller_csr_WREADY; -logic [DATA_WIDTH-1:0] sd_controller_csr_WDATA; -logic [DATA_WIDTH/8-1:0] sd_controller_csr_WSTRB; -logic sd_controller_csr_BVALID; -logic sd_controller_csr_BREADY; -logic [1:0] sd_controller_csr_BRESP; -logic sd_controller_csr_ARVALID; -logic sd_controller_csr_ARREADY; -logic [ADDR_WIDTH-1:0] sd_controller_csr_ARADDR; -logic sd_controller_csr_RVALID; -logic sd_controller_csr_RREADY; -logic [DATA_WIDTH-1:0] sd_controller_csr_RDATA; -logic [1:0] sd_controller_csr_RRESP; +logic sd_controller_ctrl_AWVALID; +logic sd_controller_ctrl_AWREADY; +logic [ADDR_WIDTH-1:0] sd_controller_ctrl_AWADDR; +logic sd_controller_ctrl_WVALID; +logic sd_controller_ctrl_WREADY; +logic [DATA_WIDTH-1:0] sd_controller_ctrl_WDATA; +logic [DATA_WIDTH/8-1:0] sd_controller_ctrl_WSTRB; +logic sd_controller_ctrl_BVALID; +logic sd_controller_ctrl_BREADY; +logic [1:0] sd_controller_ctrl_BRESP; +logic sd_controller_ctrl_ARVALID; +logic sd_controller_ctrl_ARREADY; +logic [ADDR_WIDTH-1:0] sd_controller_ctrl_ARADDR; +logic sd_controller_ctrl_RVALID; +logic sd_controller_ctrl_RREADY; +logic [DATA_WIDTH-1:0] sd_controller_ctrl_RDATA; +logic [1:0] sd_controller_ctrl_RRESP; // these are for the dma master. logic sd_controller_dma_AWVALID; @@ -235,47 +235,53 @@ cpu_wrapper u_cpu_wrapper_0( ); -axi_crossbar #( - .N_INITIATORS(2), - .N_TARGETS(4) +axilxbar #( + .NM(2), + .NS(4), + .SLAVE_ADDR({ + {32'h000001ff, 32'h00000000}, + {32'h0000ffff, 32'h0000ff00}, + {32'h0000dfff, 32'h00000200}, + {32'h0000e03f, 32'h0000e000} + }) ) u_crossbar ( - .clk(i_sysclk), - .rst(~master_reset), + .S_AXI_ACLK (i_sysclk), + .S_AXI_ARESETN (master_reset), - .ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }), - .ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }), - .ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }), - .ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }), - .ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }), - .ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }), - .ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }), - .ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }), - .ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }), - .ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }), - .ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }), - .ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }), - .ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }), - .ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }), - .ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }), - .ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }), - .ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }), - .tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }), - .tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }), - .tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }), - .tgt_rdata ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_csr_RDATA }), - .tgt_rresp ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_csr_RRESP }), - .tgt_rvalid ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_csr_RVALID }), - .tgt_rready ({ram_rready, rom_rready, sdram_RREADY, sd_controller_csr_RREADY }), - .tgt_awaddr ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_csr_AWADDR }), - .tgt_awvalid ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_csr_AWVALID }), - .tgt_awready ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_csr_AWREADY }), - .tgt_wdata ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_csr_WDATA }), - .tgt_wvalid ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_csr_WVALID }), - .tgt_wready ({ram_wready, rom_wready, sdram_WREADY, sd_controller_csr_WREADY }), - .tgt_wstrb ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_csr_WSTRB }), - .tgt_bresp ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_csr_BRESP }), - .tgt_bvalid ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_csr_BVALID }), - .tgt_bready ({ram_bready, rom_bready, sdram_BREADY, sd_controller_csr_BREADY }) + .S_AXI_ARADDR ({cpu0_ARADDR, sd_controller_dma_ARADDR }), + .S_AXI_ARVALID ({cpu0_ARVALID, sd_controller_dma_ARVALID }), + .S_AXI_ARREADY ({cpu0_ARREADY, sd_controller_dma_ARREADY }), + .S_AXI_RDATA ({cpu0_RDATA, sd_controller_dma_RDATA }), + .S_AXI_RRESP ({cpu0_RRESP, sd_controller_dma_RRESP }), + .S_AXI_RVALID ({cpu0_RVALID, sd_controller_dma_RVALID }), + .S_AXI_RREADY ({cpu0_RREADY, sd_controller_dma_RREADY }), + .S_AXI_AWADDR ({cpu0_AWADDR, sd_controller_dma_AWADDR }), + .S_AXI_AWREADY ({cpu0_AWREADY, sd_controller_dma_AWREADY }), + .S_AXI_AWVALID ({cpu0_AWVALID, sd_controller_dma_AWVALID }), + .S_AXI_WVALID ({cpu0_WVALID, sd_controller_dma_WVALID }), + .S_AXI_WREADY ({cpu0_WREADY, sd_controller_dma_WREADY }), + .S_AXI_WDATA ({cpu0_WDATA, sd_controller_dma_WDATA }), + .S_AXI_WSTRB ({cpu0_WSTRB, sd_controller_dma_WSTRB }), + .S_AXI_BRESP ({cpu0_BRESP, sd_controller_dma_BRESP }), + .S_AXI_BVALID ({cpu0_BVALID, sd_controller_dma_BVALID }), + .S_AXI_BREADY ({cpu0_BREADY, sd_controller_dma_BREADY }), + .M_AXI_ARADDR ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_ctrl_ARADDR }), + .M_AXI_ARVALID ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_ctrl_ARVALID }), + .M_AXI_ARREADY ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_ctrl_ARREADY }), + .M_AXI_RDATA ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_ctrl_RDATA }), + .M_AXI_RRESP ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_ctrl_RRESP }), + .M_AXI_RVALID ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_ctrl_RVALID }), + .M_AXI_RREADY ({ram_rready, rom_rready, sdram_RREADY, sd_controller_ctrl_RREADY }), + .M_AXI_AWADDR ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_ctrl_AWADDR }), + .M_AXI_AWVALID ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_ctrl_AWVALID }), + .M_AXI_AWREADY ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_ctrl_AWREADY }), + .M_AXI_WDATA ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_ctrl_WDATA }), + .M_AXI_WVALID ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_ctrl_WVALID }), + .M_AXI_WREADY ({ram_wready, rom_wready, sdram_WREADY, sd_controller_ctrl_WREADY }), + .M_AXI_WSTRB ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_ctrl_WSTRB }), + .M_AXI_BRESP ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_ctrl_BRESP }), + .M_AXI_BVALID ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_ctrl_BVALID }), + .M_AXI_BREADY ({ram_bready, rom_bready, sdram_BREADY, sd_controller_ctrl_BREADY }) ); @@ -417,51 +423,72 @@ sdram_controller u_sdram_controller( .o_sdr_DQM (w_sdr_DQM) ); -logic sd_controller_apb_psel; -logic sd_controller_apb_penable; -logic sd_controller_apb_pwrite; -logic [2:0] sd_controller_apb_pprot; -logic [ADDR_WIDTH-1:0] sd_controller_apb_paddr; -logic [DATA_WIDTH-1:0] sd_controller_apb_pwdata; -logic [DATA_WIDTH/8-1:0] sd_controller_apb_pstrb; -logic sd_controller_apb_pready; -logic [DATA_WIDTH-1:0] sd_controller_apb_prdata; -logic sd_controller_apb_pslverr; +logic sd_irq; +sdio_top #( + .NUMIO (1), // board as it stands is in 1 bit mode + .ADDRESS_WIDTH (32), + .DW (32), + .OPT_DMA (1), + .OPT_EMMC (0), + .OPT_SERDES (0), + .OPT_DDR (0), + .OPT_1P8V (0) // doesn't really matter but we don't need it +) u_sdio_top ( + .i_clk (i_sysclk), + .i_reset (~master_reset), + .i_hsclk ('0), // Not using serdes -axi4_lite_to_apb4 u_sd_axi_apb_converter ( - .i_clk(i_sysclk), - .i_rst(~master_reset), + .S_AXIL_AWVALID (sd_controller_ctrl_AWVALID), + .S_AXIL_AWREADY (sd_controller_ctrl_AWREADY), + .S_AXIL_AWADDR (sd_controller_ctrl_AWADDR), + .S_AXIL_AWPROT ('0), + .S_AXIL_WVALID (sd_controller_ctrl_WVALID), + .S_AXIL_WREADY (sd_controller_ctrl_WREADY), + .S_AXIL_WDATA (sd_controller_ctrl_WDATA), + .S_AXIL_WSTRB (sd_controller_ctrl_WSTRB), + .S_AXIL_BVALID (sd_controller_ctrl_BVALID), + .S_AXIL_BREADY (sd_controller_ctrl_BREADY), + .S_AXIL_BRESP (sd_controller_ctrl_BRESP), + .S_AXIL_ARVALID (sd_controller_ctrl_ARVALID), + .S_AXIL_ARREADY (sd_controller_ctrl_ARREADY), + .S_AXIL_ARADDR (sd_controller_ctrl_ARADDR), + .S_AXIL_ARPROT ('0), + .S_AXIL_RVALID (sd_controller_ctrl_RVALID), + .S_AXIL_RREADY (sd_controller_ctrl_RREADY), + .S_AXIL_RDATA (sd_controller_ctrl_RDATA), + .S_AXIL_RRESP (sd_controller_ctrl_RRESP), - .i_AWVALID(sd_controller_csr_AWVALID), - .o_AWREADY(sd_controller_csr_AWREADY), - .i_AWADDR(sd_controller_csr_AWADDR), - .i_WVALID(sd_controller_csr_AWVALID), - .o_WREADY(sd_controller_csr_WREADY), - .i_WDATA(sd_controller_csr_WDATA), - .i_WSTRB(sd_controller_csr_WSTRB), - .o_BVALID(sd_controller_csr_BVALID), - .i_BREADY(sd_controller_csr_BREADY), - .o_BRESP(sd_controller_csr_BRESP), - .i_ARVALID(sd_controller_csr_ARVALID), - .o_ARREADY(sd_controller_csr_ARREADY), - .i_ARADDR(sd_controller_csr_ARADDR), - .i_ARPROT('0), - .o_RVALID(sd_controller_csr_RVALID), - .i_RREADY(sd_controller_csr_RREADY), - .o_RDATA(sd_controller_csr_RDATA), - .o_RRESP(sd_controller_csr_RRESP), + .M_AXI_AWVALID (sd_controller_dma_AWVALID), + .M_AXI_AWREADY (sd_controller_dma_AWREADY), + .M_AXI_AWADDR (sd_controller_dma_AWADDR), + .M_AXI_AWPROT (), + .M_AXI_WVALID (sd_controller_dma_WVALID), + .M_AXI_WREADY (sd_controller_dma_WREADY), + .M_AXI_WDATA (sd_controller_dma_WDATA), + .M_AXI_WSTRB (sd_controller_dma_WSTRB), + .M_AXI_BVALID (sd_controller_dma_BVALID), + .M_AXI_BREADY (sd_controller_dma_BREADY), + .M_AXI_BRESP (sd_controller_dma_BRESP), + .M_AXI_ARVALID (sd_controller_dma_ARVALID), + .M_AXI_ARREADY (sd_controller_dma_ARREADY), + .M_AXI_ARADDR (sd_controller_dma_ARADDR), + .M_AXI_ARPROT (), + .M_AXI_RVALID (sd_controller_dma_RVALID), + .M_AXI_RREADY (sd_controller_dma_RREADY), + .M_AXI_RDATA (sd_controller_dma_RDATA), + .M_AXI_RRESP (sd_controller_dma_RRESP), - .m_apb_psel(sd_controller_apb_psel), - .m_apb_penable(sd_controller_apb_penable), - .m_apb_pwrite(sd_controller_apb_pwrite), - .m_apb_pprot(sd_controller_apb_pprot), - .m_apb_paddr(sd_controller_apb_paddr), - .m_apb_pwdata(sd_controller_apb_pwdata), - .m_apb_pstrb(sd_controller_apb_pstrb), - .m_apb_pready(sd_controller_apb_pready), - .m_apb_prdata(sd_controller_apb_prdata), - .m_apb_pslverr(sd_controller_apb_pslverr) + .i_dat (i_sd_dat), + .o_dat (o_sd_dat), + .io_dat_tristate (o_sd_dat_oe), + .i_cmd (i_sd_cmd), + .o_cmd (o_sd_cmd), + .io_cmd_tristate (o_sd_cmd_oe), + .o_ck (o_sd_clk), + .i_ds ('0), //emmc, don't care + .i_card_detect (i_sd_cd), + .o_int (sd_irq) ); endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/axi_crossbar b/hw/super6502_fpga/src/sub/axi_crossbar deleted file mode 160000 index 5c61f56..0000000 --- a/hw/super6502_fpga/src/sub/axi_crossbar +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 5c61f56e7b66853abe2a079745d1cf010bd18175 diff --git a/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv b/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv deleted file mode 100644 index a44d9b1..0000000 --- a/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_controller_wrapper.sv +++ /dev/null @@ -1,215 +0,0 @@ -module sd_controller_wrapper( - input i_clk_100, - input i_rst_100, - - input logic i_ctrl_AWVALID, - output logic o_ctrl_AWREADY, - input logic [31:0] i_ctrl_AWADDR, - input logic [2:0] i_ctrl_AWPROT, - - input logic i_ctrl_WVALID, - output logic o_ctrl_WREADY, - input logic [31:0] i_ctrl_WDATA, - input logic [3:0] i_ctrl_WSTRB, - - output logic o_ctrl_BVALID, - input logic i_ctrl_BREADY, - output logic [1:0] o_ctrl_BRESP, - - input logic i_ctrl_ARVALID, - output logic o_ctrl_ARREADY, - input logic [31:0] i_ctrl_ARADDR, - input logic [2:0] i_ctrl_ARPROT, - - output logic o_ctrl_RVALID, - input logic i_ctrl_RREADY, - output logic [31:0] o_ctrl_RDATA, - output logic [1:0] o_ctrl_RRESP, - - output logic o_dma_AWVALID, - input logic i_dma_AWREADY, - output logic [31:0] o_dma_AWADDR, - output logic [2:0] o_dma_AWPROT, - - output logic o_dma_WVALID, - input logic i_dma_WREADY, - output logic [31:0] o_dma_WDATA, - output logic [31:0] o_dma_WSTRB, - - input logic i_dma_BVALID, - output logic o_dma_BREADY, - input logic [1:0] i_dma_BRESP, - - output logic o_dma_ARVALID, - input logic i_dma_ARREADY, - output logic [31:0] o_dma_ARADDR, - output logic [2:0] o_dma_ARPROT, - - input logic i_dma_RVALID, - output logic o_dma_RREADY, - input logic [31:0] i_dma_RDATA, - input logic [1:0] i_dma_RRESP, - - input wire [3:0] sd_dat_dat_i, //Data in from SDcard - output wire [3:0] sd_dat_out_o, //Data out to SDcard - output wire sd_dat_oe_o, //SD Card tristate Data Output enable (Connects on the SoC TopLevel) - - input wire sd_cmd_dat_i, //Command in from SDcard - output wire sd_cmd_out_o, //Command out to SDcard - output wire sd_cmd_oe_o //SD Card tristate CMD Output enable (Connects on the SoC TopLevel) -); - -logic wb_reset; -logic wb_clock; - -logic [31:0] wb_ctrl_data_i; -logic [31:0] wb_ctrl_data_o; -logic [31:0] wb_ctrl_addr_i; // need to do address offset either here or in xbar -logic [3:0] wb_ctrl_sel_i; -logic wb_ctrl_we_i; -logic wb_ctrl_cyc_i; -logic wb_ctrl_stb_i; -logic wb_ctrl_ack_o; - -logic [31:0] wb_dma_adr_o; -logic [3:0] wb_dma_sel_o; -logic wb_dma_we_o; -logic [31:0] wb_dma_dat_i; -logic [31:0] wb_dma_dat_o; -logic wb_dma_cyc_o; -logic wb_dma_stb_o; -logic wb_dma_ack_i; -logic [2:0] wb_dma_cti_o; -logic [1:0] wb_dma_bte_o; - - -//axilite2wbsp -axilite2wbsp #( - .C_AXI_DATA_WIDTH(32), - .C_AXI_ADDR_WIDTH(32), - .LGFIFO(4), - .OPT_READONLY(0), - .OPT_WRITEONLY(0) -) u_axilite2wbsp ( - .i_clk (i_clk_100), - .i_axi_reset_n (~i_rst_100), - - .i_axi_awvalid (i_ctrl_AWVALID), - .o_axi_awready (o_ctrl_AWREADY), - .i_axi_awaddr (i_ctrl_AWADDR), - .i_axi_awprot (i_ctrl_AWPROT), - - .i_axi_wvalid (i_ctrl_AWVALID), - .o_axi_wready (o_ctrl_WREADY), - .i_axi_wdata (i_ctrl_WDATA), - .i_axi_wstrb (i_ctrl_WSTRB), - - .o_axi_bvalid (o_ctrl_BVALID), - .i_axi_bready (i_ctrl_BREADY), - .o_axi_bresp (o_ctrl_BRESP), - - .i_axi_arvalid (i_ctrl_ARVALID), - .o_axi_arready (o_ctrl_ARREADY), - .i_axi_araddr (i_ctrl_ARADDR), - .i_axi_arprot (i_ctrl_ARPROT), - - .o_axi_rvalid (o_ctrl_RVALID), - .i_axi_rready (i_ctrl_RREADY), - .o_axi_rdata (o_ctrl_rdata), - .o_axi_rresp (o_ctrl_rresp), - - .o_reset (wb_reset), - - .o_wb_cyc (wb_ctrl_cyc_i), - .o_wb_stb (wb_ctrl_stb_i), - .o_wb_we (wb_ctrl_we_i), - .o_wb_addr (wb_ctrl_addr_i), - .o_wb_data (wb_ctrl_data_i), - .o_wb_sel (wb_ctrl_sel_i), - .i_wb_stall ('0), - .i_wb_ack (wb_ctrl_ack_o), - .i_wb_data (wb_ctrl_data_o), - .i_wb_err ('0) -); - -//wb2axilite -wbm2axilite #( - .C_AXI_ADDR_WIDTH(32) -) u_wbm2axilite ( - .i_clk (i_clk_100), - .i_reset (wb_reset), - - .i_wb_cyc (wb_dma_cyc_o), - .i_wb_stb (wb_dma_stb_o), - .i_wb_we (wb_dma_we_o), - .i_wb_addr (wb_dma_adr_o), - .i_wb_data (wb_dma_dat_o), - .i_wb_sel (wb_dma_sel_o), - .o_wb_stall (), - .o_wb_ack (wb_dma_ack_i), - .o_wb_data (wb_dma_dat_i), - .o_wb_err (), - - .o_axi_awvalid (o_dma_AWVALID), - .i_axi_awready (i_dma_AWREADY), - .o_axi_awaddr (o_dma_AWADDR), - .o_axi_awprot (o_dma_AWPROT), - - .o_axi_wvalid (o_dma_WVALID), - .i_axi_wready (i_dma_WREADY), - .o_axi_wdata (o_dma_WDATA), - .o_axi_wstrb (o_dma_WSTRB), - - .i_axi_bvalid (i_dma_BVALID), - .o_axi_bready (o_dma_BREADY), - .i_axi_bresp (i_dma_BRESP), - - .o_axi_arvalid (o_dma_ARVALID), - .i_axi_arready (i_dma_ARREADY), - .o_axi_araddr (o_dma_ARADDR), - .o_axi_arprot (o_dma_ARPROT), - - .i_axi_rvalid (i_dma_RVALID), - .o_axi_rready (o_dma_RREADY), - .i_axi_rdata (i_dma_RDATA), - .i_axi_rresp (i_dma_RRESP) -); - -//sdc controller -sdc_controller u_sdc_controller ( - .wb_clk_i (i_clk_100), - .wb_rst_i (wb_reset), - - .wb_dat_i (wb_ctrl_data_i), - .wb_dat_o (wb_ctrl_data_o), - .wb_adr_i (wb_ctrl_addr_i), - .wb_sel_i (wb_ctrl_sel_i), - .wb_we_i (wb_ctrl_we_i), - .wb_cyc_i (wb_ctrl_cyc_i), - .wb_stb_i (wb_ctrl_stb_i), - .wb_ack_o (wb_ctrl_ack_o), - - .m_wb_adr_o (wb_dma_adr_o), - .m_wb_sel_o (wb_dma_sel_o), - .m_wb_we_o (wb_dma_we_o), - .m_wb_dat_o (wb_dma_dat_o), - .m_wb_dat_i (wb_dma_dat_i), - .m_wb_cyc_o (wb_dma_cyc_o), - .m_wb_stb_o (wb_dma_stb_o), - .m_wb_ack_i (wb_dma_ack_i), - .m_wb_cti_o (), // uhh, guys? - .m_wb_bte_o (), - - .sd_cmd_dat_i (sd_cmd_i), - .sd_cmd_dat_o (sd_cmd_o), - .sd_cmd_oe_o (sd_cmd_oe), - .sd_dat_dat_i (sd_dat_i), - .sd_dat_dat_o (sd_dat_o), - .sd_dat_oe_o (sd_dat_oe), - - .card_detect (sd_cd), - .sd_clk_o_pad (sd_clk) -); - - -endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller b/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller deleted file mode 160000 index a9a5811..0000000 --- a/hw/super6502_fpga/src/sub/sdcard_controller_wrapper/sdcard_mass_storage_controller +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a9a5811c0554400ccba33215d89d1bacd867ca9b diff --git a/hw/super6502_fpga/src/sub/sdspi b/hw/super6502_fpga/src/sub/sdspi new file mode 160000 index 0000000..78c24b8 --- /dev/null +++ b/hw/super6502_fpga/src/sub/sdspi @@ -0,0 +1 @@ +Subproject commit 78c24b8d5856f925abf7d2ffd97b09ff63301127 diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 90346fc..0f0cc9e 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,115 +1,115 @@ - + + - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - \ No newline at end of file +