diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e34f157..e1194ce 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -21,7 +21,8 @@ variables:
 
 stages:          # List of stages for jobs, and their order of execution
   - toolchain
-  - build
+  - build_sw
+  - build_hw
   - simulate
 
 build toolchain:
@@ -38,20 +39,13 @@ build toolchain:
       - sw/cc65/bin
       - sw/cc65/lib
 
-build fpga:       # This job runs in the build stage, which runs first.
-  tags:
-    - efinity
-    - linux
-  stage: build
-  script:
-    - source init_env.sh
-    - cd hw/efinix_fpga
-    - make
-
 build bios:
   tags:
     - linux
-  stage: build
+  stage: build_sw
+  artifacts:
+    paths:
+      - hw/efinix_fpga/init_hex.mem
   script:
     - source init_env.sh
     - cd sw/
@@ -62,7 +56,7 @@ build bios:
 build kernel:
   tags:
     - linux
-  stage: build
+  stage: build_sw
   script:
     - source init_env.sh
     - cd sw/
@@ -70,6 +64,18 @@ build kernel:
   dependencies:
     - build toolchain
 
+build fpga:       # This job runs in the build stage, which runs first.
+  tags:
+    - efinity
+    - linux
+  stage: build_hw
+  dependencies:
+    - build bios
+  script:
+    - source init_env.sh
+    - cd hw/efinix_fpga
+    - make
+
 
 full sim:
   when: manual
diff --git a/hw/efinix_fpga/.gitignore b/hw/efinix_fpga/.gitignore
index ef0d6e8..849df8d 100644
--- a/hw/efinix_fpga/.gitignore
+++ b/hw/efinix_fpga/.gitignore
@@ -7,3 +7,4 @@ outflow
 *.gtkw
 *.vvp
 
+.mem
\ No newline at end of file
diff --git a/hw/efinix_fpga/init_hex.mem b/hw/efinix_fpga/init_hex.mem
deleted file mode 100644
index 0fea330..0000000
--- a/hw/efinix_fpga/init_hex.mem
+++ /dev/null
@@ -1,257 +0,0 @@
-@00000000
-00 80 4C 00 00 8D 13 92 8E 14 92 8D 1A 92 8E 1B
-92 88 B9 FF FF 8D 24 92 88 B9 FF FF 8D 23 92 8C
-26 92 20 FF FF A0 FF D0 E8 60 00 00 42 FD 00 00
-00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 BA
-FD 20 2F FA 20 52 F0 58 20 69 F2 6C FC FF 20 23
-FA 00 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 AD FF
-EF A2 00 60 8D FF EF 60 20 4F F2 C9 0A D0 05 A9
-0D 20 4F F2 60 DA 5A A8 B2 04 AA A9 1B 20 4F F2
-A9 5B 20 4F F2 98 20 4F F2 A9 3B 20 4F F2 8A 20
-4F F2 A9 48 20 4F F2 7A FA 60 DA A9 1B 20 4F F2
-A9 63 20 4F F2 68 60 40 DA BA 48 E8 E8 BD 00 01
-29 10 D0 06 68 FA 20 68 F2 40 68 FA 7C BF F0 C5
-F0 C9 F0 CA F0 20 9A F0 40 40 20 68 F0 40 48 A0
-04 B1 04 09 40 20 3F F2 88 B1 04 20 3F F2 88 10
-F8 68 09 01 20 3F F2 20 1F FB 60 A2 08 A9 FF 20
-3F F2 C9 FF D0 03 CA D0 F4 60 85 0C 86 0D 20 EB
-F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 0C FB 60
-AA 20 96 FC A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
-0D CA D0 F0 60 85 0C 86 0D 20 EB F0 C9 02 B0 12
-E6 0C D0 02 E6 0C A5 0C A6 0D 20 C3 FC A9 04 20
-10 F1 60 48 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF
-20 3F F2 68 20 CE F0 20 EB F0 A8 A9 FF 20 3F F2
-A9 00 20 39 F2 A9 FF 20 3F F2 98 A2 00 60 A9 00
-20 39 F2 20 8B F1 A9 FF 20 3F F2 A9 00 20 39 F2
-A2 50 A9 FF 20 3F F2 CA D0 F8 60 A2 01 A9 C8 3A
-D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 96
-FC A5 04 85 10 A5 05 85 11 20 C7 FA A0 00 B1 10
-91 04 C8 B1 10 91 04 C8 B1 10 91 04 C8 B1 10 91
-04 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF 20 3F F2
-A9 11 A0 04 91 04 A9 00 20 CE F0 20 EB F0 C9 FF
-F0 3F 85 16 A0 00 A9 FF 20 3F F2 85 15 A5 15 C9
-FF D0 05 C8 D0 F0 80 23 A2 02 A0 00 A9 FF 20 3F
-F2 92 0C E6 0C D0 02 E6 0D 88 D0 F0 A0 00 CA D0
-EB A9 FF 20 3F F2 A9 FF 20 3F F2 A5 15 92 0E A5
-16 48 A9 FF 20 3F F2 A9 00 20 39 F2 A9 FF 20 3F
-F2 68 60 A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D
-DA EF AD DB EF 30 FB AD D9 EF 60 8D E6 EF 60 48
-8D E6 EF AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2
-00 60 AD E7 EF A2 00 60 60 20 EA FA A2 00 86 06
-86 07 A9 00 20 81 FB 20 D0 FA A9 FC A2 FD 20 90
-FA 20 31 F3 C9 00 20 2E FC D0 03 4C 98 F2 A9 F5
-A2 FD 20 90 FA 4C 25 F3 A9 EC A2 FD 20 90 FA A0
-05 20 3D FB 20 81 FB AD 00 92 AE 01 92 20 C3 FC
-A9 0C 20 4E FB 20 96 F1 A0 07 91 04 A0 07 A2 00
-B1 04 C9 00 20 34 FC D0 03 4C DC F2 A0 06 A2 00
-B1 04 C9 FE 20 34 FC F0 03 4C E5 F2 A2 00 A9 00
-D0 03 4C E9 F2 A2 00 A9 01 D0 03 4C F1 F2 4C 22
-F3 A0 06 A2 00 B1 04 A2 00 29 F0 20 15 FA D0 03
-4C 0D F3 A9 F5 A2 FD 20 90 FA 4C 22 F3 A9 DD A2
-FD 20 C3 FC A0 08 A2 00 B1 04 20 C3 FC A0 04 20
-5C FA 6C 00 92 4C 28 F3 4C 28 F3 A0 0C 20 FB F9
-60 20 F7 FA A9 00 20 AD FC 20 6E F1 4C 68 F3 A0
-00 A2 00 18 A9 01 71 04 91 04 A0 00 A2 00 B1 04
-C9 FF 20 34 FC D0 03 4C 68 F3 A9 1B A2 FE 20 90
-FA A2 00 A9 01 4C 1E F4 20 22 F4 A0 01 91 04 C9
-01 20 2E FC D0 C9 A9 01 20 4E FB 20 3F F4 A0 01
-A2 00 B1 04 C9 01 20 2E FC D0 03 4C 9C F3 A9 12
-A2 FE 20 90 FA A2 00 A9 01 4C 1E F4 A0 05 A2 00
-B1 04 C9 AA 20 2E FC D0 03 4C B3 F3 A2 00 A9 01
-4C 1E F4 A2 00 A9 00 A0 00 91 04 A0 00 A2 00 B1
-04 C9 FF 20 34 FC D0 03 4C D9 F3 A9 03 A2 FE 20
-90 FA A2 00 A9 01 4C 1E F4 20 61 F5 A0 01 91 04
-A0 01 A2 00 B1 04 C9 02 20 4D FC D0 03 4C F7 F3
-20 7E F5 A0 01 91 04 A0 00 A2 00 18 A9 01 71 04
-91 04 A0 01 A2 00 B1 04 C9 00 20 2E FC D0 AC A9
-01 20 4E FB 20 E7 F4 A2 00 A9 00 4C 1E F4 20 24
-FB 60 A2 00 A9 00 20 AD FC A2 00 86 06 86 07 A9
-00 20 81 FB A2 00 A9 94 20 43 F1 4C 3E F4 60 20
-C3 FC A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 33 F2
-A2 00 A9 FF 20 3F F2 A2 00 A9 08 20 AD FC A2 01
-A9 00 85 06 A9 00 85 07 A9 AA 20 81 FB A2 00 A9
-86 20 CE F0 A0 01 20 34 FB 20 25 F1 A2 00 A9 FF
-20 3F F2 A2 00 A9 00 20 39 F2 A2 00 A9 FF 20 3F
-F2 20 0C FB 60 20 C3 FC A2 00 A9 FF 20 3F F2 A2
-00 A9 00 20 33 F2 A2 00 A9 FF 20 3F F2 A2 00 A9
-0D 20 AD FC A2 00 86 06 86 07 A9 00 20 81 FB A2
-00 A9 00 20 CE F0 A0 01 20 34 FB 20 FA F0 A2 00
-A9 FF 20 3F F2 A2 00 A9 00 20 39 F2 A2 00 A9 FF
-20 3F F2 20 0C FB 60 20 C3 FC 20 C7 FA A2 00 A9
-FF 20 3F F2 A2 00 A9 00 20 33 F2 A2 00 A9 FF 20
-3F F2 A0 00 91 04 A0 00 A2 00 B1 04 C9 FF 20 2E
-FC D0 03 4C 27 F5 4C 19 F5 A2 00 A9 FF 20 3F F2
-C9 FF 20 2E FC D0 F2 A2 00 A9 3A 20 AD FC A2 00
-86 06 86 07 A9 00 20 81 FB A2 00 A9 00 20 CE F0
-A0 02 20 34 FB 20 25 F1 A2 00 A9 FF 20 3F F2 A2
-00 A9 00 20 39 F2 A2 00 A9 FF 20 3F F2 20 1A FB
-60 A2 00 A9 37 20 AD FC A2 00 86 06 86 07 A9 00
-20 81 FB A2 00 A9 00 20 43 F1 4C 7D F5 60 A2 00
-A9 29 20 AD FC A2 00 86 06 A9 40 85 07 A9 00 20
-81 FB A2 00 A9 00 20 43 F1 4C 9C F5 60 20 C3 FC
-20 EA FA A0 03 A2 00 B1 04 4C AC F5 A0 0E 20 FB
-F9 60 20 C3 FC A9 00 20 AD FC 20 D0 FA A2 00 A9
-00 A0 00 20 DB FC A0 01 20 34 FB E0 02 20 4D FC
-F0 03 4C D8 F5 4C 3A F6 A9 24 A2 FE 20 C3 FC A0
-06 20 34 FB A0 00 20 29 FB 20 C3 FC A0 07 A2 00
-A9 01 20 EB F9 A0 04 20 5C FA A0 02 A2 00 B1 04
-C9 1F 20 34 FC D0 03 4C 1C F6 A9 28 A2 FE 20 90
-FA A2 00 A9 00 A0 02 91 04 4C 2E F6 A2 00 A9 20
-20 68 F0 A0 02 A2 00 18 A9 01 71 04 91 04 A0 00
-A2 00 A9 01 20 EB F9 4C C6 F5 A9 28 A2 FE 20 90
-FA 20 1F FB 60 A0 00 B1 1A E6 1A D0 02 E6 1B 60
-AD 4A 92 8D 45 92 20 F1 F6 A9 45 A2 92 20 C3 FC
-20 A4 FC 4C 02 92 A5 18 38 E9 02 85 18 B0 02 C6
-19 60 AD 4F 92 D0 11 20 8F F6 4C 0E FA AD 4F 92
-D0 06 20 8F F6 4C 08 FA 20 8F F6 85 06 86 07 20
-66 F6 A0 01 B1 18 AA 88 B1 18 60 A0 00 84 0C 84
-0D B1 1A 38 E9 30 90 2C C9 0A B0 28 20 49 F6 48
-A5 0C A6 0D 06 0C 26 0D 06 0C 26 0D 65 0C 85 0C
-8A 65 0D 85 0D 06 0C 26 0D 68 65 0C 85 0C 90 D1
-E6 0D B0 CD A5 0C A6 0D 60 AC 51 92 EE 51 92 99
-52 92 60 A9 52 A2 92 18 6D 51 92 90 01 E8 4C C3
-FC A5 1C A6 1D 4C C3 FC 20 50 F6 EE 4B 92 D0 F8
-EE 4C 92 D0 F3 60 20 F1 F6 AD 66 92 AE 67 92 20
-C3 FC AD 68 92 AE 69 92 20 C3 FC 4C 02 92 84 0C
-20 81 FB 20 E3 F6 A5 0C 4C B1 FB 84 0C 20 81 FB
-20 E3 F6 A5 0C 4C F2 FB 48 A0 05 B9 18 00 99 3F
-92 88 10 F7 68 85 18 86 19 20 04 FB 85 1A 86 1B
-20 04 FB 85 1C 86 1D A9 00 A8 91 1C C8 91 1C C8
-B1 1C 8D 03 92 C8 B1 1C 8D 04 92 A5 1A 85 0C A5
-1B 85 0D A0 00 B1 1A F0 0B C9 25 F0 07 C8 D0 F5
-E6 1B D0 F1 98 18 65 1A 85 1A 90 02 E6 1B 38 E5
-0C 85 0E A5 1B E5 0D 85 0F 05 0E F0 25 20 EA FA
-A0 05 A5 1D 91 04 88 A5 1C 91 04 88 A5 0D 91 04
-88 A5 0C 91 04 88 A5 0F 91 04 88 A5 0E 91 04 20
-02 92 20 45 F6 AA D0 0B A2 05 BD 3F 92 95 18 CA
-10 F8 60 C9 25 D0 09 B1 1A C9 25 D0 09 20 49 F6
-20 53 F6 4C 6B F7 A9 00 A2 0B 9D 46 92 CA 10 FA
-B1 1A C9 2D D0 05 8E 46 92 F0 19 C9 2B D0 05 8E
-47 92 F0 10 C9 20 D0 05 8E 48 92 F0 07 C9 23 D0
-09 8E 49 92 20 49 F6 4C F0 F7 A2 20 C9 30 D0 06
-AA 20 49 F6 B1 1A 8E 4A 92 C9 2A D0 09 20 49 F6
-20 8F F6 4C 39 F8 20 9B F6 8D 4B 92 8E 4C 92 8C
-4D 92 8C 4E 92 B1 1A C9 2E D0 1B 20 49 F6 B1 1A
-C9 2A D0 09 20 49 F6 20 8F F6 4C 60 F8 20 9B F6
-8D 4D 92 8E 4E 92 B1 1A C9 7A F0 19 C9 68 F0 15
-C9 74 F0 11 C9 6A F0 08 C9 4C F0 04 C9 6C D0 0B
-A9 FF 8D 4F 92 20 49 F6 4C 66 F8 8C 51 92 A2 52
-8E 66 92 A2 92 8E 67 92 20 49 F6 C9 63 D0 0D 20
-8F F6 8D 52 92 A2 00 A9 01 4C 92 F9 C9 64 F0 04
-C9 69 D0 2D A2 00 AD 48 92 F0 02 A2 20 AD 47 92
-F0 02 A2 2B 8E 50 92 20 7D F6 A4 07 30 0B AC 50
-92 F0 06 8C 52 92 EE 51 92 A0 0A 20 1E F7 4C 89
-F9 C9 6E D0 15 20 8F F6 85 0C 86 0D A0 00 B1 1C
-91 0C C8 B1 1C 91 0C 4C 6B F7 C9 6F D0 27 20 7D
-F6 AC 49 92 F0 17 48 86 14 05 14 05 06 05 07 0D
-4D 92 0D 4E 92 F0 06 A9 30 20 D9 F6 68 A0 08 20
-1E F7 4C 89 F9 C9 70 D0 0D A2 00 8E 4F 92 E8 8E
-49 92 A9 78 D0 27 C9 73 D0 0C 20 8F F6 8D 66 92
-8E 67 92 4C 89 F9 C9 75 D0 0B 20 72 F6 A0 0A 20
-2B F7 4C 89 F9 C9 78 F0 04 C9 58 D0 29 48 AD 49
-92 F0 0A A9 30 20 D9 F6 A9 58 20 D9 F6 20 72 F6
-A0 10 20 2B F7 68 C9 78 D0 09 AD 66 92 AE 67 92
-20 1B FD 4C 89 F9 4C 6B F7 AD 66 92 AE 67 92 20
-05 FD 8D 68 92 8E 69 92 AD 4D 92 0D 4E 92 F0 15
-AE 4D 92 EC 68 92 AD 4E 92 A8 ED 69 92 B0 06 8E
-68 92 8C 69 92 38 AD 4B 92 ED 68 92 AA AD 4C 92
-ED 69 92 B0 03 A9 00 AA 49 FF 8D 4C 92 8A 49 FF
-8D 4B 92 AD 46 92 D0 03 20 FB F6 20 06 F7 AD 46
-92 F0 03 20 FB F6 4C 6B F7 A0 00 18 71 04 91 04
-48 C8 8A 71 04 91 04 AA 68 60 C8 48 18 98 65 04
-85 04 90 02 E6 05 68 60 A0 FF E0 80 B0 02 A0 00
-84 06 84 07 60 E0 00 D0 06 AA D0 03 A9 01 60 A2
-00 8A 60 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 A9
-00 85 0C A9 F0 85 0D A9 00 85 0E A9 92 85 0F A2
-CD A9 FF 85 14 A0 00 E8 F0 0D B1 0C 91 0E C8 D0
-F6 E6 0D E6 0F D0 F0 E6 14 D0 EF 60 8C 6A 92 88
-88 98 18 65 04 85 0C A6 05 90 01 E8 86 0D A0 01
-B1 0C AA 88 B1 0C 20 C3 FC A5 0C A6 0D 20 8A FD
-AC 6A 92 4C FB F9 85 0C 86 0D 20 75 F0 4C 94 FA
-85 0C 86 0D A0 00 B1 0C F0 0E C8 84 14 20 68 F0
-A4 14 D0 F2 E6 0D D0 EE 60 E0 00 D0 15 4A AA BD
-51 FE 90 05 4A 4A 4A 4A 18 29 0F AA BD 46 FE A2
-00 60 38 A9 00 AA 60 A4 04 D0 02 C6 05 C6 04 60
-A5 04 38 E9 02 85 04 90 01 60 C6 05 60 A5 04 38
-E9 04 85 04 90 01 60 C6 05 60 A5 04 38 E9 06 85
-04 90 01 60 C6 05 60 A5 04 38 E9 07 85 04 90 01
-60 C6 05 60 A0 01 B1 04 AA 88 B1 04 E6 04 F0 05
-E6 04 F0 03 60 E6 04 E6 05 60 A0 03 4C FB F9 A0
-05 4C FB F9 A0 08 4C FB F9 85 0C 86 0D A2 00 B1
-0C 60 A0 01 B1 04 AA 88 B1 04 60 A0 03 B1 04 85
-07 88 B1 04 85 06 88 B1 04 AA 88 B1 04 60 A2 00
-18 65 04 48 8A 65 05 AA 68 60 18 49 FF 69 01 48
-8A 49 FF 69 00 AA A5 06 49 FF 69 00 85 06 A5 07
-49 FF 69 00 85 07 68 60 A9 00 AA A0 00 84 06 84
-07 48 20 DD FA A0 03 A5 07 91 04 88 A5 06 91 04
-88 8A 91 04 68 88 91 04 60 85 14 20 04 FB 85 0E
-86 0F 85 10 86 11 20 96 FC 20 04 FB 85 06 86 07
-60 20 99 FB A6 07 A4 14 C0 0A D0 39 A5 06 05 0D
-05 0C D0 11 E0 80 D0 0D A0 0B B9 3A FE 91 0E 88
-10 F8 4C 29 FC 8A 10 1D A9 2D A0 00 91 0E E6 0E
-D0 02 E6 0F A5 0C A6 0D 20 5A FB 85 0C 86 0D 4C
-F5 FB 20 99 FB A9 00 48 A0 20 A9 00 06 0C 26 0D
-26 06 26 07 2A C5 14 90 04 E5 14 E6 0C 88 D0 EC
-A8 B9 2A FE 48 A5 0C 05 0D 05 06 05 07 D0 D9 A0
-00 68 91 0E F0 03 C8 D0 F8 A5 10 A6 11 60 D0 06
-A2 00 8A 60 D0 FA A2 00 A9 01 60 F0 F9 30 F7 A2
-00 8A 60 F0 02 10 EF A2 00 8A 60 F0 E9 90 E7 A2
-00 8A 60 F0 DB A2 00 8A 2A 60 20 83 FC A6 11 F0
-13 B1 0C 91 0E C8 B1 0C 91 0E C8 D0 F4 E6 0D E6
-0F CA D0 ED A6 10 F0 08 B1 0C 91 0E C8 CA D0 F8
-4C 04 FB 85 10 86 11 20 96 FC C8 B1 04 AA 86 0F
-88 B1 04 85 0E 60 A0 01 B1 04 85 0D 88 B1 04 85
-0C 4C 0C FB A9 01 4C C1 FC A0 00 B1 04 A4 04 F0
-07 C6 04 A0 00 91 04 60 C6 05 C6 04 91 04 60 A9
-00 A2 00 48 A5 04 38 E9 02 85 04 B0 02 C6 05 A0
-01 8A 91 04 68 88 91 04 60 A0 00 91 04 C8 48 8A
-91 04 68 60 85 0E 86 0F 20 96 FC B1 0C D1 0E D0
-0C AA F0 10 C8 D0 F4 E6 0D E6 0F D0 EE B0 03 A2
-FF 60 A2 01 60 85 0E 86 0F A2 00 A0 00 B1 0E F0
-08 C8 D0 F9 E6 0F E8 D0 F4 98 60 85 0C 86 0D 85
-0E 86 0F A0 00 B1 0C F0 14 20 AD FA 29 02 F0 06
-B1 0C 69 20 91 0C C8 D0 EC E6 0D D0 E8 A5 0E A6
-0F 60 20 04 FB 85 0E 86 0F E8 8E 31 92 AA E8 8E
-30 92 20 96 FC 20 04 FB 85 10 86 11 A0 00 84 14
-B1 10 18 65 0E 91 10 C8 B1 10 65 0F 91 10 CE 30
-92 F0 11 A4 14 B1 0C C8 D0 02 E6 0D 84 14 20 68
-F0 4C 6E FD CE 31 92 D0 EA 60 85 0C 86 0D A9 00
-8D 2A 92 8D 2B 92 A0 01 B1 04 AA 88 B1 04 20 C3
-FC A0 02 A9 2A 91 04 C8 A9 92 91 04 A5 0C A6 0D
-20 38 F7 AD 2A 92 AE 2B 92 60 A9 32 85 0C A9 92
-85 0D A9 00 A8 A2 00 F0 0A 91 0C C8 D0 FB E6 0D
-CA D0 F6 C0 39 F0 05 91 0C C8 D0 F7 60 62 61 64
-20 74 6F 6B 65 6E 3A 20 25 78 0A 00 53 75 63 63
-65 73 73 0A 00 45 72 72 6F 72 0A 00 53 74 61 72
-74 0A 00 6F 70 5F 63 6F 6E 64 20 65 72 72 6F 72
-0A 00 49 46 20 43 6F 6E 64 0A 00 47 6F 20 49 44
-4C 45 0A 00 25 32 78 00 0A 00 30 31 32 33 34 35
-36 37 38 39 41 42 43 44 45 46 2D 32 31 34 37 34
-38 33 36 34 38 00 00 01 02 0C 09 0A 10 40 50 A0
-D0 66 66 66 66 A6 88 88 66 66 66 66 66 66 66 66
-66 09 00 00 00 00 00 00 00 33 33 33 33 33 00 00
-00 50 55 55 25 22 22 22 22 22 22 22 22 22 02 00
-00 40 44 44 14 11 11 11 11 11 11 11 11 11 01 00
-70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 A7 F0 32 F0 A8 F0
diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index b2d283c..63fa1ed 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -9,7 +9,7 @@ TEST_PROGRAM_NAME?=loop_test
 TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
-STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
+STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb uart_irq_tb
 CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb \
 		devices_setup_code_tb
 
diff --git a/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv b/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
index 791b6bc..a83a666 100644
--- a/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
+++ b/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
@@ -23,7 +23,7 @@ end
 initial begin
     // u_sim_top.u_dut.w_int_in = 0;
     repeat (2400) @(posedge u_sim_top.r_clk_cpu);
-    for (int i = 0; i < 256; i++) begin
+    for (int i = 0; i < 128; i++) begin
         repeat (100) @(posedge u_sim_top.r_clk_cpu);
         force u_sim_top.u_dut.u_interrupt_controller.int_in = 1 << i;
         $display("Activiating interrupt %d", i);
diff --git a/hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv b/hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
index a234f5f..dd49a27 100644
--- a/hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
+++ b/hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
@@ -4,8 +4,7 @@ module interrupt_controller_tb();
 
 logic r_clk_cpu;
 
-localparam BITS_256 = 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff;
-
+localparam BITS_128 = 128'hffffffffffffffffffffffffffffffff;
 // clk_cpu
 initial begin
     r_clk_cpu <= '1;
@@ -21,10 +20,12 @@ logic [7:0] o_data;
 logic cs;
 logic rwb;
 
-logic [255:0] int_in;
+logic [127:0] int_in;
 logic int_out;
 
-interrupt_controller u_interrupt_controller(
+interrupt_controller #(
+    .N_INTERRUPTS(128)
+) u_interrupt_controller (
     .clk(r_clk_cpu),
     .reset(reset),
     .i_data(i_data),
@@ -42,8 +43,8 @@ interrupt_controller u_interrupt_controller(
 task test_edge_irq();
     $display("Testing Edge IRQ");
     do_reset();
-    set_enable(255'hff);
-    set_edge_type(255'h0);
+    set_enable(128'hff);
+    set_edge_type(128'h0);
     set_interrupts(1);
     assert (int_out == 1) else begin
         errors = errors + 1;
@@ -64,8 +65,8 @@ endtask
 task test_level_irq();
     $display("Testing level IRQ");
     do_reset();
-    set_enable(255'hff);
-    set_edge_type(255'hff);
+    set_enable(128'hff);
+    set_edge_type(128'hff);
     set_interrupts(1);
     assert (int_out == 1) else begin
         errors = errors + 1;
@@ -91,8 +92,8 @@ task test_irq_val();
     do_reset();
     set_enable('1);
     set_edge_type('1);
-    for (int i = 255; i >= 0; i--) begin
-        set_interrupts(BITS_256 << i);
+    for (int i = 127; i >= 0; i--) begin
+        set_interrupts(BITS_128 << i);
         read_irqval(irq_val);
         assert(i == irq_val) else begin
             errors = errors + 1;
@@ -100,8 +101,8 @@ task test_irq_val();
         end
     end
 
-    for (int i = 0; i < 256; i++) begin
-        set_interrupts(BITS_256 >> i);
+    for (int i = 0; i < 128; i++) begin
+        set_interrupts(BITS_128 >> i);
         read_irqval(irq_val);
         assert(int_out == 1) else begin
             errors = errors + 1;
@@ -175,21 +176,21 @@ task do_reset();
     repeat (5) @(posedge r_clk_cpu);
 endtask
 
-task set_enable(input logic [255:0] en);
-    for (int i = 0; i < 32; i++) begin
+task set_enable(input logic [127:0] en);
+    for (int i = 0; i < 16; i++) begin
         write_reg(0, 8'h20 | i);
         write_reg(1, en[8*i +: 8]);
     end
 endtask
 
-task set_edge_type(input logic [255:0] edge_type);
-    for (int i = 0; i < 32; i++) begin
+task set_edge_type(input logic [127:0] edge_type);
+    for (int i = 0; i < 16; i++) begin
         write_reg(0, 8'h40 | i);
         write_reg(1, edge_type[8*i +: 8]);
     end
 endtask
 
-task set_interrupts(logic [255:0] ints);
+task set_interrupts(logic [127:0] ints);
     int_in = ints;
     @(posedge r_clk_cpu);
 endtask
diff --git a/hw/efinix_fpga/simulation/tbs/uart_irq_tb.sv b/hw/efinix_fpga/simulation/tbs/uart_irq_tb.sv
new file mode 100644
index 0000000..e6f3ea3
--- /dev/null
+++ b/hw/efinix_fpga/simulation/tbs/uart_irq_tb.sv
@@ -0,0 +1,15 @@
+`timescale 1ns/1ps
+
+module uart_irq_tb();
+
+sim_top u_sim_top();
+
+initial begin
+    u_sim_top.u_sim_uart.tx_en = 1;
+    @(posedge u_sim_top.r_clk_cpu);
+    u_sim_top.u_sim_uart.tx_data = 8'hAA;
+    repeat (100) @(posedge u_sim_top.r_clk_cpu);
+    $finish();
+end
+
+endmodule
\ No newline at end of file
diff --git a/hw/efinix_fpga/src/interrupt_controller.sv b/hw/efinix_fpga/src/interrupt_controller.sv
index 7f54f31..c556464 100644
--- a/hw/efinix_fpga/src/interrupt_controller.sv
+++ b/hw/efinix_fpga/src/interrupt_controller.sv
@@ -1,5 +1,7 @@
-module interrupt_controller
-(
+module interrupt_controller 
+#(
+    parameter N_INTERRUPTS = 128
+)(
     input clk,
     input reset,
     input [7:0] i_data,
@@ -8,15 +10,15 @@ module interrupt_controller
     input cs,
     input rwb,
 
-    input [255:0] int_in,
+    input [N_INTERRUPTS-1:0] int_in,
     output logic int_out
 );
 
 logic w_enable_write;
 logic [7:0] w_enable_data;
-logic [255:0] w_enable_full_data;
+logic [N_INTERRUPTS-1:0] w_enable_full_data;
 
-logic [255:0] int_in_d1;
+logic [N_INTERRUPTS-1:0] int_in_d1;
 
 logic [4:0] w_byte_sel;
 
@@ -24,7 +26,7 @@ logic [7:0] irq_val;
 
 byte_sel_register #(
     .DATA_WIDTH(8),
-    .ADDR_WIDTH(32)
+    .ADDR_WIDTH(N_INTERRUPTS/8)
 ) reg_enable (
     .i_clk(~clk),
     .i_reset(reset),
@@ -40,17 +42,17 @@ logic we, re;
 assign we = cs & ~rwb;
 assign re = cs & rwb;
 
-logic [255:0] int_masked;
+logic [N_INTERRUPTS-1:0] int_masked;
 assign int_masked = int_in & w_enable_full_data;
 
 
 logic w_type_write;
 logic [7:0] w_type_data;
-logic [255:0] w_type_full_data;
+logic [N_INTERRUPTS-1:0] w_type_full_data;
 
 byte_sel_register #(
     .DATA_WIDTH(8),
-    .ADDR_WIDTH(32)
+    .ADDR_WIDTH(N_INTERRUPTS/8)
 ) reg_type (
     .i_clk(~clk),
     .i_reset(reset),
@@ -65,7 +67,7 @@ logic [7:0] cmd, cmd_next;
 
 logic w_eoi;
 
-logic [255:0] r_int, r_int_next;
+logic [N_INTERRUPTS-1:0] r_int, r_int_next;
 
 always_comb begin
     w_eoi = 0;
@@ -108,13 +110,13 @@ always_comb begin
     int_out = |r_int;
 
     irq_val = 8'hff;
-    for (int i = 255; i >= 0; i--) begin
+    for (int i = N_INTERRUPTS-1; i >= 0; i--) begin
         if (r_int[i] == 1) begin
             irq_val = i;
         end
     end
 
-    for (int i = 0; i < 256; i++) begin
+    for (int i = 0; i < N_INTERRUPTS; i++) begin
         case (w_type_full_data[i])
             0: begin    // Edge triggered
                 if (w_eoi && i == irq_val) begin
diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv
index 14c04d1..d33827e 100644
--- a/hw/efinix_fpga/src/super6502.sv
+++ b/hw/efinix_fpga/src/super6502.sv
@@ -159,6 +159,24 @@ rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
     .data(w_rom_data_out)
 );
 
+logic w_irq;
+assign cpu_irqb = ~w_irq;
+logic [127:0] w_int_in;
+
+assign w_int_in[127:2] = 0;
+
+interrupt_controller u_interrupt_controller(
+    .clk(clk_cpu),
+    .reset(~cpu_resb),
+    .i_data(cpu_data_in),
+    .o_data(w_irq_data_out),
+    .addr(w_mapped_addr[0]),
+    .cs(w_irq_cs),
+    .rwb(cpu_rwb),
+    .int_in(w_int_in),
+    .int_out(w_irq)
+);
+
 leds u_leds(
     .clk(clk_cpu),
     .i_data(cpu_data_in),
@@ -213,7 +231,7 @@ divider_wrapper u_divider(
     .addr(w_mapped_addr[2:0])
 );
 
-logic w_uart_irqb;
+logic w_uart_irq;
 
 uart_wrapper u_uart(
     .clk(clk_cpu),
@@ -226,9 +244,11 @@ uart_wrapper u_uart(
     .addr(w_mapped_addr[0]),
     .rx_i(uart_rx),
     .tx_o(uart_tx),
-    .irqb(w_uart_irqb)
+    .irq(w_uart_irq)
 );
 
+assign w_int_in[1] = w_uart_irq;
+
 spi_controller spi_controller(
     .i_clk(clk_cpu),
     .i_rst(~cpu_resb),
@@ -275,24 +295,6 @@ sdram_adapter u_sdram_adapter(
     .o_sdr_DQM(o_sdr_DQM)
 );
 
-logic w_irq;
-assign cpu_irqb = ~w_irq;
-logic [255:0] w_int_in;
-
-assign w_int_in[255:1] = 0;
-
-interrupt_controller u_interrupt_controller(
-    .clk(clk_cpu),
-    .reset(~cpu_resb),
-    .i_data(cpu_data_in),
-    .o_data(w_irq_data_out),
-    .addr(w_mapped_addr[0]),
-    .cs(w_irq_cs),
-    .rwb(cpu_rwb),
-    .int_in(w_int_in),
-    .int_out(w_irq)
-);
-
 rtc u_rtc(
     .clk(clk_cpu),
     .reset(~cpu_resb),
diff --git a/hw/efinix_fpga/src/uart_wrapper.sv b/hw/efinix_fpga/src/uart_wrapper.sv
index 3262233..3e033bd 100644
--- a/hw/efinix_fpga/src/uart_wrapper.sv
+++ b/hw/efinix_fpga/src/uart_wrapper.sv
@@ -11,7 +11,7 @@ module uart_wrapper(
     input rx_i,
     output tx_o,
 
-    output logic irqb
+    output logic irq
 );
 
 logic [7:0] status, control;
@@ -21,6 +21,8 @@ logic tx_busy, rx_busy;
 logic rx_data_valid, rx_error, rx_parity_error;
 logic baud_x16_ce;
 
+assign irq = rx_data_valid;
+
 logic tx_en;
 
 logic [7:0] tx_data, rx_data;
@@ -47,7 +49,6 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
 always_ff @(posedge clk_50) begin
     if (reset) begin
         state <= READY;
-        irqb <= '1;
     end else begin
         state <= next_state;
     end
diff --git a/sw/bios/devices/interrupt.s b/sw/bios/devices/interrupt.s
index 862ae82..1de028b 100644
--- a/sw/bios/devices/interrupt.s
+++ b/sw/bios/devices/interrupt.s
@@ -6,12 +6,11 @@
 ;
 ; Checks for a BRK instruction and returns from all valid interrupts.
 
-.import   _handle_irq
-.import _cputc, _clrscr
-
 .export   _irq_int, _nmi_int
 
-.include "io.inc65"
+
+IRQ_VECTOR = $220
+NMI_VECTOR = $222
 
 .segment  "CODE"
 
@@ -20,81 +19,9 @@
 ; ---------------------------------------------------------------------------
 ; Non-maskable interrupt (NMI) service routine
 
-_nmi_int:  RTI                    ; Return from all NMI interrupts
+_nmi_int:  jmp (NMI_VECTOR)
 
 ; ---------------------------------------------------------------------------
 ; Maskable interrupt (IRQ) service routine
 
-_irq_int:  PHX                    ; Save X register contents to stack
-           TSX                    ; Transfer stack pointer to X
-           PHA                    ; Save accumulator contents to stack
-           INX                    ; Increment X so it points to the status
-           INX                    ;   register value saved on the stack
-           LDA $100,X             ; Load status register contents
-           AND #$10               ; Isolate B status bit
-           BNE break              ; If B = 1, BRK detected
-
-; ---------------------------------------------------------------------------
-; IRQ detected, return
-
-irq:       PLA                    ; Restore accumulator contents
-           PLX                    ; Restore X register contents
-           jsr _handle_irq        ; Handle the IRQ
-           RTI                    ; Return from all IRQ interrupts
-
-; ---------------------------------------------------------------------------
-; BRK detected, stop
-
-break:
-        pla
-        plx
-        jmp (bios_table,x)
-
-
-bios_table:
-        .addr   _console_clear
-        .addr   _console_read_char
-        .addr   _console_write_char
-
-
-_console_clear:
-        jsr _clrscr
-        rti
-
-_console_read_char:
-        ; not supported
-        rti
-
-_console_write_char:
-        jsr _cputc
-        rti
-
-
-
-; What functions do we need?
-; UART
-;   clear
-;   write character
-;   read character
-; DISK
-;   init (or should it just init on boot?)
-;   read sector into memory
-; FS
-;   init (if disk init succeeds, should it always try?)
-;   find add
-
-; I think that is all we need for now?
-; How do we call the functions?
-
-; we have to call `brk` to trigger the interrupt
-; in any of the three registers we can have arguments
-; or we could have them pushed to the stack, assuming
-; the stack is in the same location
-; Or you could pass a pointer which points to an array
-; of arguments
-
-; for things like clear, read/write character, and init you don't
-; need any arguments.
-
-; jump table index needs to be in x, but also needs to be a multiple
-; of 2.
+_irq_int:  jmp (IRQ_VECTOR)
\ No newline at end of file
diff --git a/sw/bios/irq.c b/sw/bios/irq.c
deleted file mode 100644
index 9911f8d..0000000
--- a/sw/bios/irq.c
+++ /dev/null
@@ -1,11 +0,0 @@
-
-#include <stdint.h>
-#include <conio.h>
-
-#include "devices/interrupt.h"
-#include "devices/uart.h"
-
-
-
-void handle_irq() {
-}
\ No newline at end of file
diff --git a/sw/kernel/devices/interrupt.s b/sw/kernel/devices/interrupt.s
deleted file mode 100644
index 02b24ae..0000000
--- a/sw/kernel/devices/interrupt.s
+++ /dev/null
@@ -1,51 +0,0 @@
-; ---------------------------------------------------------------------------
-; interrupt.s
-; ---------------------------------------------------------------------------
-;
-; Interrupt handler.
-;
-; Checks for a BRK instruction and returns from all valid interrupts.
-
-.import   _handle_irq
-.import _cputc, _clrscr
-
-.export   _irq_int, _nmi_int
-
-.include "io.inc65"
-
-.segment  "CODE"
-
-.PC02                             ; Force 65C02 assembly mode
-
-; ---------------------------------------------------------------------------
-; Non-maskable interrupt (NMI) service routine
-
-_nmi_int:  RTI                    ; Return from all NMI interrupts
-
-; ---------------------------------------------------------------------------
-; Maskable interrupt (IRQ) service routine
-
-_irq_int:  PHX                    ; Save X register contents to stack
-           TSX                    ; Transfer stack pointer to X
-           PHA                    ; Save accumulator contents to stack
-           INX                    ; Increment X so it points to the status
-           INX                    ;   register value saved on the stack
-           LDA $100,X             ; Load status register contents
-           AND #$10               ; Isolate B status bit
-           BNE break              ; If B = 1, BRK detected
-
-; ---------------------------------------------------------------------------
-; IRQ detected, return
-
-irq:       PLA                    ; Restore accumulator contents
-           PLX                    ; Restore X register contents
-           jsr _handle_irq        ; Handle the IRQ
-           RTI                    ; Return from all IRQ interrupts
-
-; ---------------------------------------------------------------------------
-; BRK detected, stop
-
-break:
-        pla
-        plx
-        rti
\ No newline at end of file
diff --git a/sw/kernel/devices/interrupt_controller.s b/sw/kernel/devices/interrupt_controller.s
index 4c45167..6441237 100644
--- a/sw/kernel/devices/interrupt_controller.s
+++ b/sw/kernel/devices/interrupt_controller.s
@@ -9,6 +9,8 @@
 .export _disable_irq
 .export _send_eoi
 
+.import irq_int, nmi_int
+
 IRQ_CMD_ADDR    = $effc
 IRQ_DAT_ADDR    = $effd
 
@@ -19,11 +21,24 @@ IRQ_CMD_ENABLE  = $20
 IRQ_CMD_TYPE    = $40
 IRQ_CMD_EOI     = $ff
 
+IRQ_VECTOR = $220
+NMI_VECTOR = $222
+
 .code
 
 ; void init_irq();
 ; mask all IRQs, set all type to edge.
 .proc _init_interrupt_controller
+    lda #<irq_int
+    sta IRQ_VECTOR
+    lda #>irq_int
+    sta IRQ_VECTOR+1
+
+    lda #<nmi_int
+    sta NMI_VECTOR
+    lda #>nmi_int
+    sta NMI_VECTOR+1
+
     ldx #$20    ; enable
     ldy #00
     jsr cmd_all
@@ -34,7 +49,7 @@ IRQ_CMD_EOI     = $ff
 
 cmd_all:        ; Send the same value to all 32 bytes
     txa
-    add #$20
+    add #$10
     sta tmp1
 loop:
     txa
@@ -51,12 +66,10 @@ loop:
 ; void enable_irq(uint8_t type, uint8_t irqnum);
 ; in A: 
 .proc _enable_irq
-    ; Decide which byte we need to modify by dividing by 32 (>> 5)
+    ; Decide which byte we need to modify by dividing by 8 (>> 3)
     pha
     lsr
     lsr
-    lsr
-    lsr
     lsr         ; A is now bytesel
     sta tmp2    ; tmp2 is now bytesel
     add #IRQ_CMD_ENABLE
@@ -97,13 +110,12 @@ L3: sta IRQ_DAT_ADDR
 
 .endproc
 
+; TODO this is mostly the same as enable, why copy?
 .proc _disable_irq
     ; Decide which byte we need to modify by dividing by 32 (>> 5)
     pha
     lsr
     lsr
-    lsr
-    lsr
     lsr         ; A is now bytesel
     add #IRQ_CMD_ENABLE
     sta IRQ_CMD_ADDR
diff --git a/sw/kernel/devices/rtc.s b/sw/kernel/devices/rtc.s
index a9e3df7..2d66d16 100644
--- a/sw/kernel/devices/rtc.s
+++ b/sw/kernel/devices/rtc.s
@@ -14,6 +14,18 @@ RTC_IRQ_THRESHOLD   = $20
 RTC_OUTPUT          = $30
 RTC_CONTROL         = $30
 
+THRESHOLD_0         = $a0
+; THRESHOLD_1         = $0f
+THRESHOLD_1         = $00
+THRESHOLD_2         = $00
+THRESHOLD_3         = $00
+
+; IRQ_THRESHOLD_0     = $32
+IRQ_THRESHOLD_0     = $10
+IRQ_THRESHOLD_1     = $00
+IRQ_THRESHOLD_2     = $00
+IRQ_THRESHOLD_3     = $00
+
 ; void init_rtc(void);
 ; Initialize rtc and generate 50ms interrupts
 .proc _init_rtc
@@ -36,36 +48,36 @@ RTC_CONTROL         = $30
 
     lda #RTC_THRESHOLD+0    ; Set threshold to 4000 ($fa0)
     sta RTC_CMD
-    lda #$a0
+    lda #THRESHOLD_0
     sta RTC_DAT
     lda #RTC_THRESHOLD+1
     sta RTC_CMD
-    lda #$0f
+    lda #THRESHOLD_1
     sta RTC_DAT
     lda #RTC_THRESHOLD+2
     sta RTC_CMD
-    lda #$00
+    lda #THRESHOLD_2
     sta RTC_DAT
     lda #RTC_THRESHOLD+3
     sta RTC_CMD
-    lda #$00
+    lda #THRESHOLD_3
     sta RTC_DAT
 
     lda #RTC_IRQ_THRESHOLD+0    ; Set irq threshold to 50 ($32)
     sta RTC_CMD
-    lda #$32
+    lda #IRQ_THRESHOLD_0
     sta RTC_DAT
     lda #RTC_IRQ_THRESHOLD+1
     sta RTC_CMD
-    lda #$00
+    lda #IRQ_THRESHOLD_1
     sta RTC_DAT
     lda #RTC_IRQ_THRESHOLD+2
     sta RTC_CMD
-    lda #$00
+    lda #IRQ_THRESHOLD_2
     sta RTC_DAT
     lda #RTC_IRQ_THRESHOLD+3
     sta RTC_CMD
-    lda #$00
+    lda #IRQ_THRESHOLD_3
     sta RTC_DAT
 
     lda #$30
diff --git a/sw/kernel/devices/interrupt.h b/sw/kernel/interrupts/interrupt.h
similarity index 79%
rename from sw/kernel/devices/interrupt.h
rename to sw/kernel/interrupts/interrupt.h
index d0231aa..6aeadc2 100644
--- a/sw/kernel/devices/interrupt.h
+++ b/sw/kernel/interrupts/interrupt.h
@@ -6,8 +6,7 @@
 #define BUTTON  (1 << 0)
 #define UART    (1 << 1)
 
-void irq_int();
-void nmi_int();
+void register_irq(void* addr, uint8_t irqn);
 
 uint8_t irq_get_status();
 void irq_set_status(uint8_t);
diff --git a/sw/kernel/interrupts/interrupt.s b/sw/kernel/interrupts/interrupt.s
new file mode 100644
index 0000000..89e56ce
--- /dev/null
+++ b/sw/kernel/interrupts/interrupt.s
@@ -0,0 +1,51 @@
+.MACPACK generic
+
+.autoimport
+
+.import _enable_irq
+
+.export   irq_int, nmi_int
+.export _register_irq
+
+IRQ_CMD_ADDR    = $effc
+IRQ_DAT_ADDR    = $effd
+
+IRQ_CMD_READIRQ = $00
+
+
+.proc nmi_int
+rti
+.endproc
+
+
+; irq_int
+.proc irq_int
+    ; Load IRQ number
+    lda #IRQ_CMD_READIRQ
+    sta IRQ_CMD_ADDR
+    lda IRQ_DAT_ADDR
+    ; shift by 2 (oh so only 128 interrupts are supported lol)
+    lsr
+    tax
+    jmp (irq_table,x)
+    ; use that to index jump table
+.endproc
+
+; void register_irq(void* addr, uint8_t irqn);
+.proc _register_irq
+    tax
+    jsr popa
+    sta irq_table,x
+    jsr popa
+    sta irq_table+1,x
+
+    lda #$00
+    jsr pusha
+    txa
+    jsr _enable_irq
+    rts
+.endproc
+
+.data
+; interrupt handler jump table
+irq_table: .res 256
diff --git a/sw/kernel/irq.c b/sw/kernel/irq.c
index 9911f8d..6e3f7ab 100644
--- a/sw/kernel/irq.c
+++ b/sw/kernel/irq.c
@@ -2,7 +2,7 @@
 #include <stdint.h>
 #include <conio.h>
 
-#include "devices/interrupt.h"
+#include "interrupts/interrupt.h"
 #include "devices/uart.h"
 
 
diff --git a/sw/kernel/kernel.c b/sw/kernel/kernel.c
index 50564bf..b4a8f4a 100644
--- a/sw/kernel/kernel.c
+++ b/sw/kernel/kernel.c
@@ -1,8 +1,14 @@
 #include <conio.h>
 #include "devices/interrupt_controller.h"
+#include "interrupts/interrupt.h"
 #include "devices/rtc.h"
 
 
+void handle_rtc_interrupt() {
+    cputs("In IRQ interrupt!\n");
+    asm volatile ("rti");
+}
+
 int main() {
 
     cputs("Kernel\n");
@@ -19,6 +25,10 @@ int main() {
     cputs("Initialize RTC\n");
     init_rtc();
 
+    register_irq(&handle_rtc_interrupt, 0);
+
+    asm volatile("cli");
+
     // cputs("Initialize Serial\n");
     // // init_serial();
     // enable_irq(2, IRQ_EDGE);
@@ -26,4 +36,4 @@ int main() {
     while(1);
 
     return 0;
-}
\ No newline at end of file
+}
diff --git a/sw/test_code/devices_setup_test/Makefile b/sw/test_code/devices_setup_test/Makefile
index 2af39c8..8443644 100644
--- a/sw/test_code/devices_setup_test/Makefile
+++ b/sw/test_code/devices_setup_test/Makefile
@@ -5,31 +5,27 @@ LDFLAGS=-C link.ld -m $(NAME).map
 
 NAME=devices_setup_test
 
-DEVICES=../../kernel/devices
+DEVICES=$(REPO_TOP)/sw/kernel/devices
 
 BIN=$(NAME).bin
 HEX=$(NAME).hex
 
 LISTS=lists
 
-KERNEL_SRCS=rtc.s interrupt_controller.s
-KERNEL_OBJS=$(patsubst %.s,%.o,$(filter %s,$(KERNEL_SRCS)))
-
-SRCS=$(wildcard *.s) $(wildcard *.c) 
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(DEVICES)/rtc.s $(DEVICES)/interrupt_controller.s
 SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
 OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
 OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
 
 # Make sure the kernel linked to correct address, no relocation!
-all: $(KERNEL_SRCS) $(HEX)
-	rm rtc.s
-	rm interrupt_controller.s
+all: $(HEX)
 
 $(HEX): $(BIN)
 	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
 
-$(BIN): $(OBJS) $(KERNEL_OBJS)
-	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) $(KERNEL_OBJS) -o $@
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
 
 %.o: %.c $(LISTS)
 	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
@@ -40,15 +36,7 @@ $(BIN): $(OBJS) $(KERNEL_OBJS)
 $(LISTS):
 	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
 
-rtc.s: $(DEVICES)/rtc.s
-	cp $(DEVICES)/rtc.s .
-
-interrupt_controller.s: $(DEVICES)/interrupt_controller.s
-	cp $(DEVICES)/interrupt_controller.s .
-
 .PHONY: clean
 clean:
 	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
-	rm -rf $(KERNEL_SRCS)
-	rm -rf $(KERNEL_OBJS)
 
diff --git a/sw/test_code/devices_setup_test/main.s b/sw/test_code/devices_setup_test/main.s
index a380d19..74219b6 100644
--- a/sw/test_code/devices_setup_test/main.s
+++ b/sw/test_code/devices_setup_test/main.s
@@ -1,4 +1,4 @@
-.export _init, _nmi_int, _irq_int
+.export _init, nmi_int, irq_int
 
 .autoimport
 
@@ -11,8 +11,8 @@ finish: .res 1
 
 .code
 
-_nmi_int:
-_irq_int:
+nmi_int:
+irq_int:
     lda #$6d
     sta $00
 
diff --git a/sw/test_code/devices_setup_test/vectors.s b/sw/test_code/devices_setup_test/vectors.s
index 81ae6e0..73c2865 100644
--- a/sw/test_code/devices_setup_test/vectors.s
+++ b/sw/test_code/devices_setup_test/vectors.s
@@ -5,10 +5,10 @@
 ; Defines the interrupt vector table.
 
 .import    _init
-.import    _nmi_int, _irq_int
+.import    nmi_int, irq_int
 
 .segment  "VECTORS"
 
-.addr      _nmi_int    ; NMI vector
+.addr      nmi_int    ; NMI vector
 .addr      _init       ; Reset vector
-.addr      _irq_int    ; IRQ/BRK vector
\ No newline at end of file
+.addr      irq_int    ; IRQ/BRK vector
\ No newline at end of file
diff --git a/sw/test_code/irq_test/main.s b/sw/test_code/irq_test/main.s
index 7610350..31be63c 100644
--- a/sw/test_code/irq_test/main.s
+++ b/sw/test_code/irq_test/main.s
@@ -54,7 +54,7 @@ _init:
 
 cmd_all:
     txa
-    add #$20
+    add #$10
     sta tmp1
 loop:
     txa