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Increase TCP count to 2

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After removing all the inferred latches, we have enough space to have 2
TCP streams instead of just 1. Also we have way more timing slack.

Lesson learned, inferred latches are *really* bad and you should remove
them first before anything else.
This commit is contained in:
Byron Lathi
2024-10-13 20:01:37 -07:00
parent 5e8d91be53
commit 6bf7fee64b
2 changed files with 2 additions and 2 deletions
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2
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
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@@ -526,7 +526,7 @@ logic network_processor_reset;
always_ff @(posedge i_sysclk) network_processor_reset <= ~master_resetn;
network_processor #(
.NUM_TCP(1)
.NUM_TCP(2)
) u_network_processor (
.i_clk (i_sysclk),
.i_rst (network_processor_reset),

2
hw/super6502_fpga/super6502_fpga.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502_fpga" description="" last_change="1728874118" sw_version="2024.1.163" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502_fpga" description="" last_change="1728874681" sw_version="2024.1.163" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>