From 6eeecda368f7e4b1fb360cc49c7f78600343518d Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Wed, 19 Jul 2023 21:06:54 -0700
Subject: [PATCH] Add wait states during refresh

---
 hw/efinix_fpga/sdram_adapter.sv | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/hw/efinix_fpga/sdram_adapter.sv b/hw/efinix_fpga/sdram_adapter.sv
index cd5af34..c9c1603 100644
--- a/hw/efinix_fpga/sdram_adapter.sv
+++ b/hw/efinix_fpga/sdram_adapter.sv
@@ -13,6 +13,8 @@ module sdram_adapter(
     output logic [7:0] o_data,  // Output data
 
     output o_sdr_init_done,
+    
+    output o_wait,
 
     output o_sdr_CKE,
     output o_sdr_n_CS,
@@ -100,6 +102,32 @@ always @(posedge i_sysclk) begin
         o_data <= _data;
 end
 
+logic r_wait;
+logic _r_wait;
+assign o_wait = r_wait;
+
+// we need to assert rdy low until a falling edge if a reset happens
+
+always @(posedge i_sysclk or posedge i_arst) begin
+    if (i_arst == '1) begin
+        r_wait <= '0;
+        _r_wait <= '0;
+    end else begin
+        if (o_dbg_ref_req) begin
+            r_wait <= '1;
+        end else if (i_cpuclk == '1) begin
+            _r_wait <= '1;
+        end
+
+        if (i_cpuclk == '0) begin
+            if (_r_wait) begin
+                _r_wait <= '0;
+                r_wait <= '0;
+            end
+        end
+    end
+end
+
 //because of timing issues, We really need to trigger
 //the write on the falling edge of phi2. There is a 2ns
 //delay between the rising edge of phi2 and data valid
@@ -220,6 +248,8 @@ logic [31:0] o_dbg_DATA_in;
 logic o_sdr_init_done;
 logic [3:0] o_sdr_state;
 
+assign o_ref_req = o_dbg_ref_req;
+
 
 sdram_controller u_sdram_controller(
     .i_arst(i_arst),      //Positive Controller Reset