Add rtc code test

2023-11-19 11:58:37 -08:00
parent 77629b16ce
commit 7002aeebe6
9 changed files with 210 additions and 5 deletions
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -146,4 +146,19 @@ interrupt_controller_code sim:
    - cd hw/efinix_fpga/simulation
    - make clean
    - TEST_PROGRAM_NAME=mapper_test make interrupt_controller_code_tb
-    - ./interrupt_controller_code_tb
+    - ./interrupt_controller_code_tb
+
+rtc_code sim:
+  tags:
+    - linux
+    - iverilog
+  stage: simulate
+  artifacts:
+    paths:
+      - hw/efinix_fpga/simulation/interrupt_controller_code.vcd
+  script:
+    - source init_env.sh
+    - cd hw/efinix_fpga/simulation
+    - make clean
+    - TEST_PROGRAM_NAME=rtc_test make rtc_code_tb
+    - ./rtc_code_tb