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Add rtc code test

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This commit is contained in:
Byron Lathi
2023-11-19 11:58:37 -08:00
parent 77629b16ce
commit 7002aeebe6
9 changed files with 210 additions and 5 deletions
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2
hw/efinix_fpga/simulation/Makefile
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@@ -10,7 +10,7 @@ TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb
#TODO implement something like sources.list

23
hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv Normal file
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@@ -0,0 +1,23 @@
`timescale 1ns/1ps
module rtc_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
endmodule