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SD_command assembly rewrite

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This commit is contained in:
Byron Lathi
2023-07-23 16:25:13 -07:00
parent 5ca5fca29b
commit 709c60cf36
5 changed files with 188 additions and 416 deletions
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278
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,12 +3,12 @@
{
"name": "la0",
"type": "la",
"uuid": "68ae6f6753aa4c41b26baf6770f0d8e4",
"uuid": "fc5ad0b7db9846e2b64719110e7975d8",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 8192,
"data_depth": 16384,
"input_pipeline": 1,
"probes": [
{
@@ -36,31 +36,11 @@
"width": 16,
"probe_type": 1
},
{
"name": "cpu_nmib",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_irqb",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_data_out",
"width": 8,
"probe_type": 1
},
{
"name": "cpu_phi2",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_rdy",
"width": 1,
"probe_type": 1
},
{
"name": "spi_clk",
"width": 1,
@@ -85,16 +65,6 @@
"name": "spi_controller/active",
"width": 1,
"probe_type": 1
},
{
"name": "spi_controller/r_clock_counter",
"width": 9,
"probe_type": 1
},
{
"name": "spi_controller/r_baud_rate",
"width": 8,
"probe_type": 1
}
]
}
@@ -362,209 +332,35 @@
},
{
"name": "la0_probe5",
"net": "cpu_nmib",
"path": []
},
{
"name": "la0_probe6",
"net": "cpu_irqb",
"path": []
},
{
"name": "la0_probe7[0]",
"net": "cpu_data_out[0]",
"path": []
},
{
"name": "la0_probe7[1]",
"net": "cpu_data_out[1]",
"path": []
},
{
"name": "la0_probe7[2]",
"net": "cpu_data_out[2]",
"path": []
},
{
"name": "la0_probe7[3]",
"net": "cpu_data_out[3]",
"path": []
},
{
"name": "la0_probe7[4]",
"net": "cpu_data_out[4]",
"path": []
},
{
"name": "la0_probe7[5]",
"net": "cpu_data_out[5]",
"path": []
},
{
"name": "la0_probe7[6]",
"net": "cpu_data_out[6]",
"path": []
},
{
"name": "la0_probe7[7]",
"net": "cpu_data_out[7]",
"path": []
},
{
"name": "la0_probe8",
"net": "cpu_phi2",
"path": []
},
{
"name": "la0_probe9",
"net": "cpu_rdy",
"path": []
},
{
"name": "la0_probe10",
"name": "la0_probe6",
"net": "spi_clk",
"path": []
},
{
"name": "la0_probe11",
"name": "la0_probe7",
"net": "spi_mosi",
"path": []
},
{
"name": "la0_probe12",
"name": "la0_probe8",
"net": "sd_cs",
"path": []
},
{
"name": "la0_probe13",
"name": "la0_probe9",
"net": "spi_miso",
"path": []
},
{
"name": "la0_probe14",
"name": "la0_probe10",
"net": "active",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[0]",
"net": "r_clock_counter[0]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[1]",
"net": "r_clock_counter[1]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[2]",
"net": "r_clock_counter[2]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[3]",
"net": "r_clock_counter[3]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[4]",
"net": "r_clock_counter[4]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[5]",
"net": "r_clock_counter[5]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[6]",
"net": "r_clock_counter[6]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[7]",
"net": "r_clock_counter[7]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe15[8]",
"net": "r_clock_counter[8]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[0]",
"net": "r_baud_rate[0]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[1]",
"net": "r_baud_rate[1]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[2]",
"net": "r_baud_rate[2]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[3]",
"net": "r_baud_rate[3]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[4]",
"net": "r_baud_rate[4]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[5]",
"net": "r_baud_rate[5]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[6]",
"net": "r_baud_rate[6]",
"path": [
"spi_controller"
]
},
{
"name": "la0_probe16[7]",
"net": "r_baud_rate[7]",
"path": [
"spi_controller"
]
}
]
}
@@ -578,7 +374,7 @@
],
"session": {
"wizard": {
"data_depth": 8192,
"data_depth": 16384,
"capture_control": false,
"selected_nets": [
{
@@ -625,32 +421,6 @@
"net_idx_left": 15,
"net_idx_right": 0
},
{
"name": "cpu_nmib",
"width": 1,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_irqb",
"width": 1,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_data_out",
"width": 8,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 7,
"net_idx_right": 0
},
{
"name": "cpu_phi2",
"width": 1,
@@ -659,14 +429,6 @@
"child": [],
"path": []
},
{
"name": "cpu_rdy",
"width": 1,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "spi_clk",
"width": 1,
@@ -708,30 +470,6 @@
"path": [
"spi_controller"
]
},
{
"name": "r_clock_counter",
"width": 9,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [
"spi_controller"
],
"net_idx_left": 8,
"net_idx_right": 0
},
{
"name": "r_baud_rate",
"width": 8,
"clk_domain": "clk_50",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [
"spi_controller"
],
"net_idx_left": 7,
"net_idx_right": 0
}
],
"top_module": "super6502",

290
hw/efinix_fpga/init_hex.mem
View File

@@ -2,151 +2,151 @@
8D 0E 02 8E 0F 02 8D 15 02 8E 16 02 88 B9 FF FF
8D 1F 02 88 B9 FF FF 8D 1E 02 8C 21 02 20 FF FF
A0 FF D0 E8 60 A2 FF 9A D8 A9 F0 85 00 A9 7E 85
01 20 CD F8 20 38 F7 20 45 F0 58 20 E6 F0 6C FC
FF 20 2C F7 00 A0 00 F0 07 A9 45 A2 F0 4C 00 02
60 AD FF EF A2 00 60 8D FF EF 60 20 CC F0 C9 0A
D0 05 A9 0D 20 CC F0 60 DA 5A A8 B2 00 AA A9 1B
20 CC F0 A9 5B 20 CC F0 98 20 CC F0 A9 3B 20 CC
F0 8A 20 CC F0 A9 48 20 CC F0 7A FA 60 DA A9 1B
20 CC F0 A9 63 20 CC F0 68 60 40 DA BA 48 E8 E8
BD 00 01 29 10 D0 06 68 FA 20 E5 F0 40 4C AD F0
A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D DA EF AD
DB EF 30 FB AD D9 EF 60 8D E6 EF 60 48 8D E6 EF
AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2 00 60 AD
E7 EF A2 00 60 60 20 B8 F7 A2 00 86 02 86 03 A9
00 20 38 F8 20 91 F7 A9 14 A2 F9 20 6F F7 20 28
F1 C9 00 20 50 F8 D0 03 4C 15 F1 A9 F0 A2 F8 20
6F F7 4C 1C F1 A9 05 A2 F9 20 6F F7 4C 1F F1 4C
1F F1 A0 0C 20 1F F7 60 20 C5 F7 A9 00 20 80 F8
20 9A F2 4C 5F F1 A0 00 A2 00 18 A9 01 71 00 91
00 A0 00 A2 00 B1 00 C9 FF 20 56 F8 D0 03 4C 5F
F1 A9 36 A2 F9 20 6F F7 A2 00 A9 01 4C 96 F2 20
B1 F4 A0 01 91 00 C9 01 20 50 F8 D0 C9 A2 00 A9
00 A0 06 20 C4 F8 A0 07 20 09 F8 E0 03 D0 02 C9
E8 20 6F F8 F0 03 4C 8C F1 4C 98 F1 A0 06 A2 00
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A0 01 A2 00 B1 00 C9 01 20 50 F8 D0 03 4C BE F1
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2
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun July 23 2023 14:51:17" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Sun July 23 2023 16:23:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>