From 73419736204df95816d0ed0c653b44a1e2f7c802 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 12 Oct 2022 18:50:42 -0500 Subject: [PATCH] Redo shield, removing FPGA Don't have the FPGA on the shield, just have it be a board that plugs into the FPGA. Don't mind the component and footprint choices yet, I still need to figure out exactly which parts to use. --- hw/efinix_shield/.gitignore | 29 + hw/efinix_shield/efinix_shield.kicad_pcb | 1058 ++++++++- hw/efinix_shield/efinix_shield.kicad_pro | 104 +- hw/efinix_shield/efinix_shield.kicad_sch | 2644 +++++++++++----------- hw/efinix_shield/fp-info-cache | 1 - hw/efinix_shield/fpga.kicad_sch | 10 + hw/efinix_shield/io.kicad_sch | 2108 +++++++++++++++++ 7 files changed, 4682 insertions(+), 1272 deletions(-) create mode 100644 hw/efinix_shield/.gitignore delete mode 100644 hw/efinix_shield/fp-info-cache create mode 100644 hw/efinix_shield/fpga.kicad_sch create mode 100644 hw/efinix_shield/io.kicad_sch diff --git a/hw/efinix_shield/.gitignore b/hw/efinix_shield/.gitignore new file mode 100644 index 0000000..a63bc0e --- /dev/null +++ b/hw/efinix_shield/.gitignore @@ -0,0 +1,29 @@ +# For PCBs designed using KiCad: https://www.kicad.org/ +# Format documentation: https://kicad.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*-backups +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/hw/efinix_shield/efinix_shield.kicad_pcb b/hw/efinix_shield/efinix_shield.kicad_pcb index 28b47a1..e8d4763 100644 --- a/hw/efinix_shield/efinix_shield.kicad_pcb +++ b/hw/efinix_shield/efinix_shield.kicad_pcb @@ -1,2 +1,1058 @@ (kicad_pcb (version 20211014) (generator pcbnew) -) \ No newline at end of file + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "GND") + (net 2 "/VGA_RED") + (net 3 "/VGA_GREEN") + (net 4 "/VGA_BLUE") + (net 5 "unconnected-(J1-Pad4)") + (net 6 "unconnected-(J1-Pad9)") + (net 7 "unconnected-(J1-Pad11)") + (net 8 "unconnected-(J1-Pad12)") + (net 9 "Net-(J1-Pad13)") + (net 10 "Net-(J1-Pad14)") + (net 11 "unconnected-(J1-Pad15)") + (net 12 "VDD") + (net 13 "unconnected-(J3-Pad3)") + (net 14 "unconnected-(J3-Pad4)") + (net 15 "unconnected-(J3-Pad5)") + (net 16 "unconnected-(J3-Pad6)") + (net 17 "unconnected-(J3-Pad7)") + (net 18 "unconnected-(J3-Pad8)") + (net 19 "unconnected-(J3-Pad9)") + (net 20 "unconnected-(J3-Pad10)") + (net 21 "unconnected-(J3-Pad11)") + (net 22 "unconnected-(J3-Pad12)") + (net 23 "unconnected-(J3-Pad13)") + (net 24 "unconnected-(J3-Pad14)") + (net 25 "unconnected-(J3-Pad15)") + (net 26 "unconnected-(J3-Pad16)") + (net 27 "unconnected-(J3-Pad17)") + (net 28 "unconnected-(J3-Pad18)") + (net 29 "unconnected-(J3-Pad19)") + (net 30 "unconnected-(J3-Pad20)") + (net 31 "unconnected-(J3-Pad21)") + (net 32 "unconnected-(J3-Pad22)") + (net 33 "unconnected-(J3-Pad23)") + (net 34 "unconnected-(J3-Pad24)") + (net 35 "unconnected-(J3-Pad25)") + (net 36 "unconnected-(J3-Pad26)") + (net 37 "unconnected-(J3-Pad27)") + (net 38 "unconnected-(J3-Pad28)") + (net 39 "unconnected-(J3-Pad29)") + (net 40 "unconnected-(J3-Pad30)") + (net 41 "unconnected-(J3-Pad31)") + (net 42 "unconnected-(J3-Pad32)") + (net 43 "unconnected-(J3-Pad33)") + (net 44 "/VGA_HS") + (net 45 "/VGA_VS") + (net 46 "unconnected-(RN1-Pad4)") + (net 47 "unconnected-(RN1-Pad5)") + (net 48 "/VGA_RED_2") + (net 49 "/VGA_RED_3") + (net 50 "unconnected-(RN2-Pad4)") + (net 51 "unconnected-(RN2-Pad5)") + (net 52 "/VGA_GREEN_2") + (net 53 "/VGA_GREEN_3") + (net 54 "Net-(RN3-Pad2)") + (net 55 "unconnected-(RN3-Pad4)") + (net 56 "unconnected-(RN3-Pad5)") + (net 57 "/VGA_RED_0") + (net 58 "/VGA_RED_1") + (net 59 "Net-(RN4-Pad2)") + (net 60 "unconnected-(RN4-Pad4)") + (net 61 "unconnected-(RN4-Pad5)") + (net 62 "/VGA_GREEN_0") + (net 63 "/VGA_GREEN_1") + (net 64 "unconnected-(RN5-Pad4)") + (net 65 "unconnected-(RN5-Pad5)") + (net 66 "/VGA_BLUE_2") + (net 67 "/VGA_BLUE_3") + (net 68 "unconnected-(RN6-Pad4)") + (net 69 "unconnected-(RN6-Pad5)") + (net 70 "/VGA_BLUE_0") + (net 71 "/VGA_BLUE_1") + (net 72 "unconnected-(U1-Pad1)") + (net 73 "unconnected-(U1-Pad2)") + (net 74 "unconnected-(U1-Pad3)") + (net 75 "unconnected-(U1-Pad4)") + (net 76 "unconnected-(U1-Pad5)") + (net 77 "unconnected-(U1-Pad6)") + (net 78 "unconnected-(U1-Pad7)") + (net 79 "unconnected-(U1-Pad8)") + (net 80 "unconnected-(U1-Pad9)") + (net 81 "unconnected-(U1-Pad10)") + (net 82 "unconnected-(U1-Pad11)") + (net 83 "unconnected-(U1-Pad12)") + (net 84 "unconnected-(U1-Pad13)") + (net 85 "unconnected-(U1-Pad14)") + (net 86 "unconnected-(U1-Pad15)") + (net 87 "unconnected-(U1-Pad16)") + (net 88 "unconnected-(U1-Pad17)") + (net 89 "unconnected-(U1-Pad18)") + (net 90 "unconnected-(U1-Pad19)") + (net 91 "unconnected-(U1-Pad20)") + (net 92 "unconnected-(U1-Pad21)") + (net 93 "unconnected-(U1-Pad22)") + (net 94 "unconnected-(U1-Pad23)") + (net 95 "unconnected-(U1-Pad24)") + (net 96 "unconnected-(U1-Pad25)") + (net 97 "unconnected-(U1-Pad26)") + (net 98 "unconnected-(U1-Pad27)") + (net 99 "unconnected-(U1-Pad28)") + (net 100 "unconnected-(U1-Pad29)") + (net 101 "unconnected-(U1-Pad30)") + (net 102 "unconnected-(U1-Pad31)") + (net 103 "unconnected-(U1-Pad32)") + (net 104 "unconnected-(U2-Pad1)") + (net 105 "Net-(U2-Pad2)") + (net 106 "unconnected-(U2-Pad3)") + (net 107 "unconnected-(U2-Pad4)") + (net 108 "unconnected-(U2-Pad5)") + (net 109 "unconnected-(U2-Pad6)") + (net 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2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf") + (tags "15-pin D-Sub connector horizontal angled 90deg THT male pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm") + (property "Sheetfile" "efinix_shield.kicad_sch") + (property "Sheetname" "") + (path "/97e40c45-0497-47e2-9b07-32e14687d031") + (attr through_hole) + (fp_text reference "J1" (at 4.315 -2.61) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 5747ece3-7bbe-451b-bb04-23f133bf0654) + ) + (fp_text value "DB15_Female_HighDensity_MountingHoles" (at 4.315 14.89) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 7cdb5268-f469-4409-ad6e-13a6a9f81267) + ) + (fp_text user "${REFERENCE}" (at 4.315 10.39) (layer "F.Fab") + (effects (font (size 1 1) (thickness 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43.18) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 "GND") (pinfunction "Pin_35") (pintype "passive") (tstamp 0a7ea22f-c882-41c3-8d9d-b2d7e4d288c3)) + (pad "36" thru_hole oval (at -2.54 43.18) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 "GND") (pinfunction "Pin_36") (pintype "passive") (tstamp 2344ca06-d027-473d-bc22-d69f01433d83)) + (model "${KICAD6_3DMODEL_DIR}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x18_P2.54mm_Vertical.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + +) diff --git a/hw/efinix_shield/efinix_shield.kicad_pro b/hw/efinix_shield/efinix_shield.kicad_pro index 7893105..0427438 100644 --- a/hw/efinix_shield/efinix_shield.kicad_pro +++ b/hw/efinix_shield/efinix_shield.kicad_pro @@ -2,26 +2,120 @@ "board": { "design_settings": { "defaults": { - "board_outline_line_width": 0.1, - "copper_line_width": 0.2, + "board_outline_line_width": 0.09999999999999999, + "copper_line_width": 0.19999999999999998, + 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"silk_text_thickness": 0.15, + "silk_text_upright": false, + "zones": { + "45_degree_only": false, + "min_clearance": 0.508 + } }, "diff_pair_dimensions": [], "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "copper_edge_clearance": "error", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint_type_mismatch": "error", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + 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