Move mapper into src folder

hw/efinix_fpga/src/mapper.sv

@@ -0,0 +1,55 @@
+module mapper(
+    input clk,
+    input rst,
+
+    input [15:0] cpu_addr,
+    output logic [24:0] sdram_addr,
+
+    input cs,
+    input rwb,
+
+    input [7:0] i_data,
+    output logic [7:0] o_data
+);
+
+logic [12:0] map [16];
+
+logic [15:0] base_addr;
+
+assign base_addr = cpu_addr - 16'hefb7;
+
+logic en;
+
+always_comb begin
+    if (!en) begin
+        sdram_addr = {9'b0, cpu_addr};
+    end else begin
+        sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (rst) begin
+        en <= '0;
+        for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
+            map[a] = a;
+        end
+    end else begin
+        if (~rwb & cs) begin
+            if (base_addr == 16'h32) begin
+                en <= i_data[0];
+            end else begin
+                if (!base_addr[0]) begin
+                    map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
+                end else begin
+                    map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
+                end
+            end
+        end
+    end
+end
+
+// each each entry is 4k and total address space is 64M,
+// so we need 2^14 possible entries
+
+endmodule

hw/efinix_fpga/super6502.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Mon Sep 18 2023 07:52:10 PM" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Mon Sep 18 2023 10:43:38 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />
@@ -19,6 +19,7 @@
         <efx:design_file name="src/crc7.sv" version="default" library="default" />
         <efx:design_file name="src/rom.sv" version="default" library="default" />
         <efx:design_file name="src/spi_controller.sv" version="default" library="default" />
+        <efx:design_file name="src/mapper.sv" version="default" library="default" />
         <efx:top_vhdl_arch name="" />
     </efx:design_info>
     <efx:constraint_info>