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Update network_processor docs

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Byron Lathi
2024-08-16 07:54:10 -07:00
parent 6320af16ec
commit 7ba9658560
1 changed files with 17 additions and 31 deletions
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48
hw/super6502_fpga/src/sub/network_processor/doc/network_processor.md
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@@ -4,17 +4,7 @@ The network processor terminates TCP connections.
## Theory of Operation
The idea behind this network processor is that the configuration is stored in
a context buffer rather than being written to device configuration registers.
This like the IP addresses, ports, TCP state, flow control window, congestion
window, sequence numbers, etc. are stored in this context buffer.
The context buffer can be created once by software when the connection is
created, and is then managed by hardware until the connection is closed.
The other interface to the core is through the packet DMA interface. The packets
contain a simple header which contains the instruction for the core, the context
pointer, the protocol, and the length of the data.
Configuration is loaded statically into one of the available TCP
## Components
@@ -25,6 +15,11 @@ communication between the RX control and TX control. The most important thing th
the TCP State manager does is request the socket structures from memory, and load
these values into the RX and TX control, and vice-versa.
When the TCP State Manager sees i_tx_ctx_ptr_valid, it will read i_tx_ctx_ptr and then
DMA that struct into it's local memory. It will then look up the port in the CAM. If
the port is not present, it will write it. If the CAM is full, then we set a flag in
the context saying that the socket was not opened successfully.
#### Clock and Reset
@@ -36,34 +31,25 @@ these values into the RX and TX control, and vice-versa.
|-----------|------------|
| rst_n | General Reset |
#### Bus Interfaces
#### Regfile Inputs
All of the registers go through the tcp state manager.
| Bus Name | Type and Purpose |
| -------------- | ---------------- |
| cfg_apb | APB Configuration |
| ctx_dma_m_axil | Context DMA Master |
#### Other Signals
| Signal Name | Direction | Description |
| ----------- | --------- | ----------- |
| o_send_syn | O | Tells TX control to send a syn packet. If o_send_ack is also valid, then send a syn_ack packet |
| o_send_ack | O | Tells TX control to send an ack packet |
| o_send_fin | O | Tells TX control to send a fin packet. If o_send_ack is also valid, then send a fin_ack packet |
| o_send_type | O | Type of packet to create |
| o_send_valid | O | Send a packet |
| o_seq_num | O | Current sequence number |
| i_seq_num | I | Next sequence number |
| i_seq_num_we | I | Write new sequence number |
| o_ack_num | O | Current ack number |
| i_ack_num | I | Next ack number |
| i_ack_num_we | I | Write new ack number |
| i_ctx_addr | I | Context pointer from TX control |
| i_ctx_valid| I | Context pointer is valid |
| o_cam_key | O | Key to write to CAM (port) |
| o_cam_val | O | Value to write to CAM (pointer) |
| i_cam_val | I | Value read from CAM |
| i_cam_hit | I | Value read from CAM is valid |
| o_cam_we | O | Write value to CAM |
| o_cam_re | O | Read value from CAM |
| i_tx_ctx_ptr | I | Context pointer from TX Control |
| i_tx_ctx_ptr_valid | I | Conext pointer is valid |
| i_rx_port | I | RX Port input |
| i_rx_port_valid | I | RX Port Valid |
| i_recvd_type | I | Received packet type from RX control. Bitmask from packet. |
| i_recvd_valid | I | Recieved type valid |
| o_tx_port | O | TX port output to TX Packet Gen |
| o_tx_ip | O | TX IP Address |
| o_rx_port | O | RX port output to RX Parser |
| o_rx_ip | O | RX IP. Local IP of device |