diff --git a/hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv b/hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv index 6ea1f90..ab8531c 100644 --- a/hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv +++ b/hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv @@ -20,4 +20,30 @@ always begin # 1; end +localparam increment = 3; + +logic [7:0] prev; +initial prev = '0; + +always @(u_sim_top.w_cpu_addr) begin + if ( + u_sim_top.w_cpu_addr == 16'h1 && + u_sim_top.w_cpu_we == '1 + ) begin + if (u_sim_top.w_cpu_data_from_cpu <= prev) begin + $display("Value didn't increment!"); + $display("Bad finish!"); + $finish_and_return(-1); + end + prev = u_sim_top.w_cpu_data_from_cpu; + $display("print1: %x", u_sim_top.w_cpu_data_from_cpu); + end +end + +initial begin + repeat (5000) @(posedge u_sim_top.r_clk_cpu); + $display("Timed out"); + $finish_and_return(-1); +end + endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv index 6e4d8aa..14c04d1 100644 --- a/hw/efinix_fpga/src/super6502.sv +++ b/hw/efinix_fpga/src/super6502.sv @@ -112,7 +112,7 @@ always_comb begin w_divider_cs = w_mapped_addr >= 16'hefe8 && w_mapped_addr <= 16'hefef; w_uart_cs = w_mapped_addr >= 16'hefe6 && w_mapped_addr <= 16'hefe7; w_spi_cs = w_mapped_addr >= 16'hefd8 && w_mapped_addr <= 16'hefdb; - w_leds_cs = w_mapped_addr == 16'hefff; + w_leds_cs = w_mapped_addr == 16'hefd7; w_sdram_cs = ~( w_rom_cs | @@ -146,7 +146,7 @@ always_comb begin else if (w_irq_cs) cpu_data_out = w_irq_data_out; else if (w_rtc_cs) - cpu_data_out = w_rtc_cs; + cpu_data_out = w_rtc_data_out; else if (w_sdram_cs) cpu_data_out = w_sdram_data_out; else @@ -289,7 +289,7 @@ interrupt_controller u_interrupt_controller( .addr(w_mapped_addr[0]), .cs(w_irq_cs), .rwb(cpu_rwb), - .int_in(int_in), + .int_in(w_int_in), .int_out(w_irq) ); diff --git a/sw/test_code/rtc_test/main.s b/sw/test_code/rtc_test/main.s index 68d7259..f403e0d 100644 --- a/sw/test_code/rtc_test/main.s +++ b/sw/test_code/rtc_test/main.s @@ -10,11 +10,26 @@ RTC_DAT = $efff .zeropage finish: .res 1 +print: .res 1 +iters: .res 1 .code _nmi_int: _irq_int: + lda #$30 + sta RTC_CMD + lda RTC_DAT + sta print + + lda iters + inc + cmp #$10 + bge @end + sta iters + rti + +@end: lda #$6d sta finish @@ -48,9 +63,16 @@ _init: ; Set IRQ Threshold lda #$20 sta RTC_CMD - lda #$02 + lda #$04 sta RTC_DAT + lda #$30 + sta RTC_CMD + lda #$03 + sta RTC_DAT + + stz iters + cli wait: