From 7cb3183f85e10ed4232e6c9edc5fefcb522c53b5 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 17 Mar 2022 17:12:43 -0500
Subject: [PATCH] Add sdram to address decode test

---
 hw/fpga/hvl/cs_testbench.sv | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index d89ce93..e13a923 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -6,12 +6,13 @@ timeprecision 1ns;
 
 logic [15:0] addr;
 logic ram_cs;
+logic sdram_cs;
 logic rom_cs;
 logic hex_cs;
 logic uart_cs;
 logic irq_cs;
 
-int cs_count = ram_cs + rom_cs + hex_cs + uart_cs;
+int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs;
 
 addr_decode dut(.*);
 
@@ -23,11 +24,16 @@ initial begin : TEST_VECTORS
         assert(cs_count < 2)
         else
             $error("Multiple chip selects present!");
-        if (i < 16'h7ff0) begin
+        if (i < 16'h4000) begin
             assert(ram_cs == '1)
             else
                 $error("Bad CS! addr=%4x should have ram_cs!", addr);
         end
+        if (i >= 16'h4000 && i < 16'h7ff0) begin
+            assert(sdram_cs == '1)
+            else
+                $error("Bad CS! addr=%4x should have sdram_cs!", addr);
+        end
         if (i >= 16'h7ff0 && i < 16'h7ff4) begin
             assert(hex_cs == '1)
             else