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Add sdram to address decode test

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This commit is contained in:
Byron Lathi
2022-03-17 17:12:43 -05:00
parent 7619c7c54f
commit 7cb3183f85
1 changed files with 8 additions and 2 deletions
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10
hw/fpga/hvl/cs_testbench.sv
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@@ -6,12 +6,13 @@ timeprecision 1ns;
logic [15:0] addr; logic [15:0] addr;
logic ram_cs; logic ram_cs;
logic sdram_cs;
logic rom_cs; logic rom_cs;
logic hex_cs; logic hex_cs;
logic uart_cs; logic uart_cs;
logic irq_cs; logic irq_cs;
int cs_count = ram_cs + rom_cs + hex_cs + uart_cs; int cs_count = ram_cs + sdram_cs + rom_cs + hex_cs + uart_cs;
addr_decode dut(.*); addr_decode dut(.*);
@@ -23,11 +24,16 @@ initial begin : TEST_VECTORS
assert(cs_count < 2) assert(cs_count < 2)
else else
$error("Multiple chip selects present!"); $error("Multiple chip selects present!");
if (i < 16'h7ff0) begin if (i < 16'h4000) begin
assert(ram_cs == '1) assert(ram_cs == '1)
else else
$error("Bad CS! addr=%4x should have ram_cs!", addr); $error("Bad CS! addr=%4x should have ram_cs!", addr);
end end
if (i >= 16'h4000 && i < 16'h7ff0) begin
assert(sdram_cs == '1)
else
$error("Bad CS! addr=%4x should have sdram_cs!", addr);
end
if (i >= 16'h7ff0 && i < 16'h7ff4) begin if (i >= 16'h7ff0 && i < 16'h7ff4) begin
assert(hex_cs == '1) assert(hex_cs == '1)
else else