From 194c4b456f4595fabc946bf60db0cd6efec66802 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 5 Apr 2022 17:10:42 -0500
Subject: [PATCH 01/11] Add memory mapper.

Based on the 74ls610 but with some slight changes.

The memory mapper works by having a 16x12 ram array. The top 4 bits of
the address are used to index into this array, and the resulting word
replaces those top 4 bits. In this way, a 16 bit address is replaced
with a 24 bit address.

As of now there is no way to write 12 bit values though, so currently
we are using 20 bit addresses.

There is a chip select line that allows you to write into the ram array,
and another chip select that allows you to write to the control word.
Currently the control word is just a single bit, the enable bit.

When not enabled, the 4 index bits are passed straight through, and the higher
bits of the address are replaced with 0, a sort of identity map. Once
enabled, it operates as described above.

Since the bottom 12 bits are left unchanged, the page size is 4kb.

There are no protections so far, but might be added later, as well as
the ability to actually use all 12 bits.
---
 hw/fpga/addr_decode.sv   |  6 ++++-
 hw/fpga/memory_mapper.sv | 53 ++++++++++++++++++++++++++++++++++++++++
 hw/fpga/sdram.sv         |  4 +--
 hw/fpga/super6502.qsf    |  1 +
 hw/fpga/super6502.sv     | 44 +++++++++++++++++++++++++--------
 5 files changed, 95 insertions(+), 13 deletions(-)
 create mode 100644 hw/fpga/memory_mapper.sv

diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv
index 01c32cb..2d012d0 100644
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -5,7 +5,9 @@ module addr_decode(
     output logic hex_cs,
     output logic uart_cs,
     output logic irq_cs,
-    output logic board_io_cs
+    output logic board_io_cs,
+	output logic mm_cs1,
+	output logic mm_cs2
 );
 
 assign rom_cs = addr >= 16'h8000;
@@ -13,6 +15,8 @@ assign sdram_cs = addr < 16'h7ff0;
 assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
 assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
 assign board_io_cs = addr == 16'h7ff6;
+assign mm_cs2 = addr == 16'h7ff7;
+assign mm_cs1 = addr >= 16'h7ff8 && addr < 16'h7ffc;
 assign irq_cs  = addr == 16'h7fff;
 
 endmodule
diff --git a/hw/fpga/memory_mapper.sv b/hw/fpga/memory_mapper.sv
new file mode 100644
index 0000000..193911a
--- /dev/null
+++ b/hw/fpga/memory_mapper.sv
@@ -0,0 +1,53 @@
+/*
+ *	This is based off of the 74LS610, but is not identical.
+	Some of the inputs are flipped so that they are all active high,
+	and some outputs are reordered.
+	Notably, when MM is low, MA is present on MO0-MO4, not 8 to 11.
+ */
+
+module memory_mapper(
+	input clk,
+
+	input rw,
+	input cs,
+
+	input MM_cs,
+
+	input [3:0] RS,
+
+	input [3:0] MA,
+
+	input logic [11:0] data_in,
+	output logic [11:0] data_out,
+
+	output logic [11:0] MO
+);
+
+logic [11:0] RAM [16];
+
+logic MM;
+
+
+always_ff @(posedge clk) begin
+	if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
+		MM = |data_in;
+	end
+
+	if (cs & ~rw) begin					// write to registers
+		RAM[RS] <= data_in;
+	end else if (cs & rw) begin			// read registers
+		data_out <= RAM[RS];
+	end
+end
+
+
+always_comb begin
+	if (MM) begin						// normal mode
+		MO = RAM[MA];
+	end else begin						// passthrough mode
+		MO = {8'b0, MA};
+	end
+end
+
+endmodule
+
diff --git a/hw/fpga/sdram.sv b/hw/fpga/sdram.sv
index 522596f..6b28f40 100644
--- a/hw/fpga/sdram.sv
+++ b/hw/fpga/sdram.sv
@@ -2,7 +2,7 @@ module sdram(
     input rst,
     input clk_50,
     input cpu_clk,
-    input [15:0] addr,
+    input [23:0] addr,
     input sdram_cs,
     input rwb,
     input [7:0] data_in,
@@ -84,4 +84,4 @@ sdram_platform u0 (
     .sdram_wire_we_n(DRAM_WE_N)                          //.we_n
 );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hw/fpga/super6502.qsf b/hw/fpga/super6502.qsf
index 09cd0fc..fdb7289 100644
--- a/hw/fpga/super6502.qsf
+++ b/hw/fpga/super6502.qsf
@@ -350,6 +350,7 @@ set_location_assignment PIN_V22 -to DRAM_LDQM
 set_location_assignment PIN_U22 -to DRAM_RAS_N
 set_location_assignment PIN_J21 -to DRAM_UDQM
 set_location_assignment PIN_V20 -to DRAM_WE_N
+set_global_assignment -name SYSTEMVERILOG_FILE memory_mapper.sv
 set_global_assignment -name SYSTEMVERILOG_FILE board_io.sv
 set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
 set_global_assignment -name QIP_FILE sdram_platform/synthesis/sdram_platform.qip
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 896a501..01cf4b8 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -3,15 +3,15 @@ module super6502(
     input                   clk_50,
     input   logic           rst_n,
     input   logic           button_1,
-    
+
     input   logic [15:0]    cpu_addr,
     inout   logic [7:0]     cpu_data,
-    
+
     input   logic           cpu_vpb,
     input   logic           cpu_mlb,
     input   logic           cpu_rwb,
     input   logic           cpu_sync,
-    
+
     output  logic           cpu_led,
     output  logic           cpu_resb,
     output  logic           cpu_rdy,
@@ -20,9 +20,9 @@ module super6502(
     output  logic           cpu_phi2,
     output  logic           cpu_be,
     output  logic           cpu_nmib,
-    
+
     output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
-    
+
     input   logic           UART_RXD,
     output  logic           UART_TXD,
 
@@ -42,7 +42,7 @@ module super6502(
     output             DRAM_CAS_N,
     output             DRAM_RAS_N
   );
-  
+
 logic rst;
 assign rst = ~rst_n;
 
@@ -60,6 +60,7 @@ logic [7:0] sdram_data_out;
 logic [7:0] uart_data_out;
 logic [7:0] irq_data_out;
 logic [7:0] board_io_data_out;
+logic [7:0] mm_data_out;
 
 logic sdram_cs;
 logic rom_cs;
@@ -67,6 +68,8 @@ logic hex_cs;
 logic uart_cs;
 logic irq_cs;
 logic board_io_cs;
+logic mm_cs1;
+logic mm_cs2;
 
 cpu_clk cpu_clk(
 	.inclk0(clk_50),
@@ -84,6 +87,23 @@ assign cpu_be = '1;
 assign cpu_nmib = '1;
 assign cpu_irqb = irq_data_out == 0;
 
+logic [11:0] mm_MO;
+
+logic [23:0] mm_address;
+assign mm_address = {mm_MO, cpu_addr[11:0]};
+
+memory_mapper memory_mapper(
+	.clk(clk),
+	.rw(cpu_rwb),
+	.cs(mm_cs1),
+	.MM_cs(mm_cs2),
+	.RS(cpu_addr[3:0]),
+	.MA(cpu_addr[15:12]),
+	.data_in(cpu_data_in),
+	.data_out(mm_data_out),
+	.MO(mm_MO)
+);
+
 addr_decode decode(
     .addr(cpu_addr),
     .sdram_cs(sdram_cs),
@@ -91,7 +111,9 @@ addr_decode decode(
     .hex_cs(hex_cs),
     .uart_cs(uart_cs),
     .irq_cs(irq_cs),
-    .board_io_cs(board_io_cs)
+    .board_io_cs(board_io_cs),
+	.mm_cs1(mm_cs1),
+	.mm_cs2(mm_cs2)
 );
 
 
@@ -106,6 +128,8 @@ always_comb begin
         cpu_data_out = irq_data_out;
     else if (board_io_cs)
         cpu_data_out = board_io_data_out;
+	else if (mm_cs1)
+		cpu_data_out = mm_data_out;
     else
         cpu_data_out = 'x;
 end
@@ -115,7 +139,7 @@ sdram sdram(
     .rst(rst),
     .clk_50(clk_50),
     .cpu_clk(cpu_phi2),
-    .addr(cpu_addr),
+    .addr(mm_address),
     .sdram_cs(sdram_cs),
     .rwb(cpu_rwb),
     .data_in(cpu_data_in),
@@ -193,6 +217,6 @@ always_ff @(posedge clk_50) begin
     end
 
 end
- 
+
 endmodule
- 
\ No newline at end of file
+

From 2600a23e59636f5fbdf4776113caad4cdbbf70ea Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 5 Apr 2022 17:20:23 -0500
Subject: [PATCH 02/11] Add memory_mapper testbench

This testbench simply creates the memory mapper, adds a mapping to the
first entry, and then makes sure the addresses are correct after
enabling and disabling the memory mapper.
---
 hw/fpga/hvl/mm_testbench.sv                 | 80 +++++++++++++++++++++
 hw/fpga/simulation/modelsim/mm_testbench.do | 17 +++++
 2 files changed, 97 insertions(+)
 create mode 100644 hw/fpga/hvl/mm_testbench.sv
 create mode 100644 hw/fpga/simulation/modelsim/mm_testbench.do

diff --git a/hw/fpga/hvl/mm_testbench.sv b/hw/fpga/hvl/mm_testbench.sv
new file mode 100644
index 0000000..777552c
--- /dev/null
+++ b/hw/fpga/hvl/mm_testbench.sv
@@ -0,0 +1,80 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk_50, clk, cs;
+logic rw, MM_cs;
+logic [3:0] RS, MA;
+logic [7:0] data_in;
+logic [7:0] data_out;
+
+logic [11:0] MO;
+
+logic [11:0] _data_in;
+assign _data_in = {4'h0, data_in};
+
+logic [11:0] _data_out;
+assign data_out = _data_out[7:0];
+
+logic [15:0] cpu_addr;
+logic [23:0] mm_address;
+assign MA = cpu_addr[15:12];
+assign mm_address = {MO, cpu_addr[11:0]};
+
+memory_mapper dut(
+	.data_in(_data_in),
+	.data_out(_data_out),
+	.*
+);
+
+always #1 clk_50 = clk_50 === 1'b0;
+always #100 clk = clk === 1'b0;
+
+task write_reg(logic [3:0] addr, logic [7:0] data);
+	@(negedge clk);
+	cs <= '1;
+	RS <= addr;
+	data_in <= data;
+	rw <= '0;
+	@(posedge clk);
+	cs <= '0;
+	rw <= '1;
+	@(negedge clk);
+endtask
+
+task enable(logic [7:0] data);
+	@(negedge clk);
+	MM_cs <= '1;
+	rw <= '0;
+	data_in <= data;
+	@(posedge clk);
+	rw <= '1;
+	MM_cs <= '0;
+	@(negedge clk);
+endtask
+
+initial begin
+	cpu_addr <= 16'h0abc;
+	write_reg(4'h0, 8'hcc);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h000abc) else begin
+		$error("Bad address before enable!");
+	end
+
+	enable(1);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h0ccabc) else begin
+		$error("Bad address after enable!");
+	end
+
+	enable(0);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h000abc) else begin
+		$error("Bad address after enable!");
+	end
+	$finish();
+end
+
+endmodule
diff --git a/hw/fpga/simulation/modelsim/mm_testbench.do b/hw/fpga/simulation/modelsim/mm_testbench.do
new file mode 100644
index 0000000..6627a55
--- /dev/null
+++ b/hw/fpga/simulation/modelsim/mm_testbench.do
@@ -0,0 +1,17 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../memory_mapper.sv}
+vlog -sv -work work  {../../hvl/mm_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+

From d9474df5235a419a6da4ec8d1d3bf94553aed425 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 5 Apr 2022 17:27:28 -0500
Subject: [PATCH 03/11] Update cs_testbench.sv

---
 hw/fpga/hvl/cs_testbench.sv | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index 7624080..cae35da 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -11,8 +11,10 @@ logic hex_cs;
 logic board_io_cs;
 logic uart_cs;
 logic irq_cs;
+logic mm_cs2;
+logic mm_cs1;
 
-int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs;
+int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1;
 
 addr_decode dut(.*);
 
@@ -44,6 +46,16 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have board_io_cs!", addr);
         end
+        if (i == 16'h7ff7) begin
+            assert(mm_cs2 == '1)
+            else
+                $error("Bad CS! addr=%4x should have mm_cs2!", addr);
+        end
+        if (i >= 16'h7ff8 && i < 16'h7ffc) begin
+            assert(mm_cs1 == '1)
+            else
+                $error("Bad CS! addr=%4x should have mm_cs1!", addr);
+        end
         if (i == 16'h7fff) begin
             assert(irq_cs == '1)
             else

From 3c44be8e6d86574d157a019bb7810d19b34f4d93 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 5 Apr 2022 17:31:24 -0500
Subject: [PATCH 04/11] Add mm_testbench to gitlab-ci

---
 .gitlab-ci.yml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 16e5ba1..25079d4 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -38,3 +38,10 @@ test-sw:
   script:
     - cd sw/
     - make test
+
+test_mm:
+    stage: test
+    image: bslathi19/modelsim_18.1:lite
+    script:
+      - cd hw/fpga/simulation/modelsim/
+      - vsim -do "do mm_testbench.do"

From a15dde0e89f8a97050d073db0e331e6c171808e2 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 10:32:28 -0500
Subject: [PATCH 05/11] Add memory mapper software interface

Adds functions to read and write mappings, as well as enable and disable
the memory mapper.

This also moves increases the io space by 16 bytes.
---
 hw/fpga/addr_decode.sv |  4 ++--
 sw/io.inc65            |  3 +++
 sw/mapper.h            | 12 ++++++++++++
 sw/mapper.s            | 32 ++++++++++++++++++++++++++++++++
 4 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 sw/mapper.h
 create mode 100644 sw/mapper.s

diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv
index 2d012d0..32e1aa3 100644
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -11,12 +11,12 @@ module addr_decode(
 );
 
 assign rom_cs = addr >= 16'h8000;
-assign sdram_cs = addr < 16'h7ff0;
+assign sdram_cs = addr < 16'h7fe0;
+assign mm_cs1 = addr >= 16'h7fe0 && addr < 16'h7ff0;
 assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
 assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
 assign board_io_cs = addr == 16'h7ff6;
 assign mm_cs2 = addr == 16'h7ff7;
-assign mm_cs1 = addr >= 16'h7ff8 && addr < 16'h7ffc;
 assign irq_cs  = addr == 16'h7fff;
 
 endmodule
diff --git a/sw/io.inc65 b/sw/io.inc65
index 61b079b..5e87bc2 100644
--- a/sw/io.inc65
+++ b/sw/io.inc65
@@ -8,4 +8,7 @@ UART_STATUS = UART + 1
 LED         = $7ff6
 SW          = LED
 
+MM_CTRL		= $7ff7
+MM_DATA		= $7fe0
+
 IRQ_STATUS  = $7fff
diff --git a/sw/mapper.h b/sw/mapper.h
new file mode 100644
index 0000000..8276b60
--- /dev/null
+++ b/sw/mapper.h
@@ -0,0 +1,12 @@
+#ifndef _MAPPER_H
+#define _MAPPER_H
+
+#include <stdint.h>
+
+void mapper_enable(uint8_t en);
+
+uint8_t mapper_read(uint8_t addr);
+void mapper_write(uint8_t data, uint8_t addr);
+
+#endif
+
diff --git a/sw/mapper.s b/sw/mapper.s
new file mode 100644
index 0000000..2ed1bc0
--- /dev/null
+++ b/sw/mapper.s
@@ -0,0 +1,32 @@
+.include "io.inc65"
+
+.importzp sp, sreg
+
+.export _mapper_enable
+.export _mapper_read, _mapper_write
+
+.autoimport on
+
+.code
+
+
+; void mapper_enable(uint8_t en)
+_mapper_enable:
+	sta MM_CTRL
+	rts
+
+_mapper_read:
+	phx
+	tax
+	lda MM_DATA,x
+	ldx #$00
+	rts
+
+_mapper_write:
+	phx
+	tax
+	jsr popa
+	sta MM_DATA,x
+	plx
+	rts
+

From be497ecaa968a892ceda95574d7c948d4ea44e87 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 10:35:16 -0500
Subject: [PATCH 06/11] Add reset input to memory mapper

Upon reset the memory mapper is automatically disabled, but the mappings
are not cleared.
---
 hw/fpga/memory_mapper.sv | 21 +++++++++++++--------
 hw/fpga/super6502.sv     |  1 +
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/hw/fpga/memory_mapper.sv b/hw/fpga/memory_mapper.sv
index 193911a..00858d7 100644
--- a/hw/fpga/memory_mapper.sv
+++ b/hw/fpga/memory_mapper.sv
@@ -7,6 +7,7 @@
 
 module memory_mapper(
 	input clk,
+	input rst,
 
 	input rw,
 	input cs,
@@ -29,15 +30,19 @@ logic MM;
 
 
 always_ff @(posedge clk) begin
-	if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
-		MM = |data_in;
-	end
+    if (rst) begin
+        MM <= '0;
+    end else begin
+        if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
+            MM = |data_in;
+        end
 
-	if (cs & ~rw) begin					// write to registers
-		RAM[RS] <= data_in;
-	end else if (cs & rw) begin			// read registers
-		data_out <= RAM[RS];
-	end
+        if (cs & ~rw) begin					// write to registers
+            RAM[RS] <= data_in;
+        end else if (cs & rw) begin			// read registers
+            data_out <= RAM[RS];
+        end
+    end
 end
 
 
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 01cf4b8..f4587f3 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -94,6 +94,7 @@ assign mm_address = {mm_MO, cpu_addr[11:0]};
 
 memory_mapper memory_mapper(
 	.clk(clk),
+    .rst(rst),
 	.rw(cpu_rwb),
 	.cs(mm_cs1),
 	.MM_cs(mm_cs2),

From 35040860e7fc8f0cf399163c476f763a8ee19efc Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 10:36:50 -0500
Subject: [PATCH 07/11] Identity map memory upon reset

Upon reset the mapper is set to identity map and then enabled.
---
 sw/main.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/sw/main.c b/sw/main.c
index 1979789..ba39470 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -3,6 +3,7 @@
 
 #include "board_io.h"
 #include "uart.h"
+#include "mapper.h"
 
 int main() {
     int i;
@@ -13,6 +14,14 @@ int main() {
     clrscr();
     cprintf("Hello, world!\n");
 
+	for (i = 0; i < 16; i++){
+		cprintf("Mapping %1xxxx to %2xxxx\n", i, i);
+		mapper_write(i, i);
+	}
+
+	cprintf("Enabling Mapper\n");
+	mapper_enable(1);
+
     while (1) {
 
         sw = sw_read();

From 74346212093baaf0b3af701e1f8ff0ec96f72151 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 10:40:11 -0500
Subject: [PATCH 08/11] Update cs_testbench.sv

---
 hw/fpga/hvl/cs_testbench.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index cae35da..7feaf66 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -26,7 +26,7 @@ initial begin : TEST_VECTORS
         assert(cs_count < 2)
         else
             $error("Multiple chip selects present!");
-        if (i < 16'h7ff0) begin
+        if (i < 16'h7fe0) begin
             assert(sdram_cs == '1)
             else
                 $error("Bad CS! addr=%4x should have sdram_cs!", addr);
@@ -51,7 +51,7 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have mm_cs2!", addr);
         end
-        if (i >= 16'h7ff8 && i < 16'h7ffc) begin
+        if (i >= 16'h7fe0 && i < 16'h7ff0) begin
             assert(mm_cs1 == '1)
             else
                 $error("Bad CS! addr=%4x should have mm_cs1!", addr);

From 5548f9d02a61e2e30d93a84af6f1642747c82003 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 10:48:10 -0500
Subject: [PATCH 09/11] Update mm_testbench

---
 hw/fpga/hvl/mm_testbench.sv                 | 5 +++++
 hw/fpga/simulation/modelsim/mm_testbench.do | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/hw/fpga/hvl/mm_testbench.sv b/hw/fpga/hvl/mm_testbench.sv
index 777552c..b498337 100644
--- a/hw/fpga/hvl/mm_testbench.sv
+++ b/hw/fpga/hvl/mm_testbench.sv
@@ -6,6 +6,7 @@ timeprecision 1ns;
 
 logic clk_50, clk, cs;
 logic rw, MM_cs;
+logic rst;
 logic [3:0] RS, MA;
 logic [7:0] data_in;
 logic [7:0] data_out;
@@ -56,6 +57,10 @@ task enable(logic [7:0] data);
 endtask
 
 initial begin
+	rst <= '1;
+	repeat(5) @(posedge clk);
+	rst <= '0;
+
 	cpu_addr <= 16'h0abc;
 	write_reg(4'h0, 8'hcc);
 	$display("Address: %x", mm_address);
diff --git a/hw/fpga/simulation/modelsim/mm_testbench.do b/hw/fpga/simulation/modelsim/mm_testbench.do
index 6627a55..9cdf649 100644
--- a/hw/fpga/simulation/modelsim/mm_testbench.do
+++ b/hw/fpga/simulation/modelsim/mm_testbench.do
@@ -15,3 +15,10 @@ add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
 onfinish stop
 run -all
 
+if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
+    echo Warning
+    quit -f -code 0
+}
+
+quit -code [coverage attribute -name TESTSTATUS -concise]
+

From 2f79a00000df997f19bbe4b8192c7311cca6d143 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 12:32:51 -0500
Subject: [PATCH 10/11] Decode physical addresses instead of virtual.

address decoding is now performed on the translated address which comes
from the memory mapper, instead of the address coming directly from the
cpu.

This means that you can access the full amount of ram at any address
that it is mapped to.
---
 hw/fpga/addr_decode.sv      | 18 +++++++++---------
 hw/fpga/hvl/cs_testbench.sv |  8 ++++----
 hw/fpga/super6502.sv        |  8 ++++----
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/hw/fpga/addr_decode.sv b/hw/fpga/addr_decode.sv
index 32e1aa3..a145fcc 100644
--- a/hw/fpga/addr_decode.sv
+++ b/hw/fpga/addr_decode.sv
@@ -1,5 +1,5 @@
 module addr_decode(
-    input logic [15:0] addr,
+    input logic [23:0] addr,
     output logic sdram_cs,
     output logic rom_cs,
     output logic hex_cs,
@@ -10,13 +10,13 @@ module addr_decode(
 	output logic mm_cs2
 );
 
-assign rom_cs = addr >= 16'h8000;
-assign sdram_cs = addr < 16'h7fe0;
-assign mm_cs1 = addr >= 16'h7fe0 && addr < 16'h7ff0;
-assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
-assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
-assign board_io_cs = addr == 16'h7ff6;
-assign mm_cs2 = addr == 16'h7ff7;
-assign irq_cs  = addr == 16'h7fff;
+assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
+assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
+assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
+assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
+assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
+assign board_io_cs = addr == 24'h007ff6;
+assign mm_cs2 = addr == 24'h007ff7;
+assign irq_cs  = addr == 24'h007fff;
 
 endmodule
diff --git a/hw/fpga/hvl/cs_testbench.sv b/hw/fpga/hvl/cs_testbench.sv
index 7feaf66..a6e1072 100644
--- a/hw/fpga/hvl/cs_testbench.sv
+++ b/hw/fpga/hvl/cs_testbench.sv
@@ -4,7 +4,7 @@ timeunit 10ns;
 
 timeprecision 1ns;
 
-logic [15:0] addr;
+logic [23:0] addr;
 logic sdram_cs;
 logic rom_cs;
 logic hex_cs;
@@ -20,13 +20,13 @@ addr_decode dut(.*);
 
 initial begin : TEST_VECTORS
 
-    for (int i = 0; i < 2**16; i++) begin
+    for (int i = 0; i < 2**24; i++) begin
         addr <= i;
         #1
         assert(cs_count < 2)
         else
             $error("Multiple chip selects present!");
-        if (i < 16'h7fe0) begin
+        if (i < 16'h7fe0 || i >= 24'h010000) begin
             assert(sdram_cs == '1)
             else
                 $error("Bad CS! addr=%4x should have sdram_cs!", addr);
@@ -61,7 +61,7 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have irq_cs!", addr);
         end
-        if (i >= 2**15) begin
+        if (i >= 2**15 && i < 24'h010000) begin
             assert(rom_cs == '1)
             else
                 $error("Bad CS! addr=%4x should have rom_cs!", addr);
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index f4587f3..fdfdafa 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -89,8 +89,8 @@ assign cpu_irqb = irq_data_out == 0;
 
 logic [11:0] mm_MO;
 
-logic [23:0] mm_address;
-assign mm_address = {mm_MO, cpu_addr[11:0]};
+logic [23:0] mm_addr;
+assign mm_addr = {mm_MO, cpu_addr[11:0]};
 
 memory_mapper memory_mapper(
 	.clk(clk),
@@ -106,7 +106,7 @@ memory_mapper memory_mapper(
 );
 
 addr_decode decode(
-    .addr(cpu_addr),
+    .addr(mm_addr),
     .sdram_cs(sdram_cs),
     .rom_cs(rom_cs),
     .hex_cs(hex_cs),
@@ -140,7 +140,7 @@ sdram sdram(
     .rst(rst),
     .clk_50(clk_50),
     .cpu_clk(cpu_phi2),
-    .addr(mm_address),
+    .addr(mm_addr),
     .sdram_cs(sdram_cs),
     .rwb(cpu_rwb),
     .data_in(cpu_data_in),

From 0752cc4b8cda40c60912d24e54453b9a0699626f Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 7 Apr 2022 12:43:47 -0500
Subject: [PATCH 11/11] do a little test to see if memory mapping works

This code creates a shared mapping in high ram, makes sure that that
works, and also makes sure that the memory which is mapped over is left
unchanged.
---
 sw/main.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/sw/main.c b/sw/main.c
index ba39470..4f894d8 100644
--- a/sw/main.c
+++ b/sw/main.c
@@ -22,6 +22,30 @@ int main() {
 	cprintf("Enabling Mapper\n");
 	mapper_enable(1);
 
+	cprintf("Writing 0xcccc to 0x4000\n");
+	*(unsigned int*)(0x4000) = 0xcccc;
+
+	cprintf("Writing 0xdddd to 0x5000\n");
+	*(unsigned int*)(0x5000) = 0xdddd;
+
+	cprintf("Mapping %1xxxx to %2xxxx\n", 4, 16);
+	mapper_write(16, 4);
+
+	cprintf("Mapping %1xxxx to %2xxxx\n", 5, 16);
+	mapper_write(16, 5);
+
+	cprintf("Writing 0xa5a5 to 0x4000\n");
+	*(unsigned int*)(0x4000) = 0xa5a5;
+
+	cprintf("Reading from 0x5000: %x\n", *(unsigned int*)(0x5000));
+
+	cprintf("Resetting map\n");
+	mapper_write(4, 4);
+	mapper_write(5, 5);
+
+	cprintf("Reading from 0x4000: %x\n", *(unsigned int*)(0x4000));
+	cprintf("Reading from 0x5000: %x\n", *(unsigned int*)(0x5000));
+
     while (1) {
 
         sw = sw_read();