Change divider to pipelined version

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The pipelining allows the cpu to run at a faster clock speed but results
in latency. At the current 2 MHz, there is 1 cycle of latency which is
negligible because the 6502 cannot do sequential data memory accesses.

In the future, there will have to be some sort of status flag or
interrupt showing that the divider is ready.

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This commit is contained in:

Byron Lathi

2023-01-05 19:21:00 -05:00

parent 5f6657a227

commit 8181a3a583

7 changed files with 490 additions and 657 deletions

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hw/efinix_fpga/debug_profile.wizard.json

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