Change divider to pipelined version

The pipelining allows the cpu to run at a faster clock speed but results
in latency. At the current 2 MHz, there is 1 cycle of latency which is
negligible because the 6502 cannot do sequential data memory accesses.

In the future, there will have to be some sort of status flag or
interrupt showing that the divider is ready.

hw/efinix_fpga/ip/divider/divider.v

@@ -43,7 +43,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 
-`define IP_UUID _1d82aa757d4b4554a855552eadc85243
+`define IP_UUID _e54826097db04c8995c0c56653e54765
 `define IP_NAME_CONCAT(a,b) a``b
 `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
 module divider (
@@ -62,7 +62,7 @@ output rfd
 .WIDTHD (16),
 .DREPRESENTATION ("UNSIGNED"),
 .PIPELINE (0),
-.LATENCY (0)
+.LATENCY (16)
 ) u_divider(
 .numer ( numer ),
 .denom ( denom ),

hw/efinix_fpga/ip/divider/divider_define.vh

@@ -48,4 +48,4 @@ localparam WIDTHN = 16;
 localparam WIDTHD = 16;
 localparam DREPRESENTATION = "UNSIGNED";
 localparam PIPELINE = 0;
-localparam LATENCY = 0;
+localparam LATENCY = 16;

hw/efinix_fpga/ip/divider/settings.json

@@ -18,7 +18,7 @@
         "WIDTHD": "16",
         "DREPRESENTATION": "0",
         "PIPELINE": "0",
-        "LATENCY": "0"
+        "LATENCY": "16"
     },
     "output": {
         "external_source_source": [
@@ -29,5 +29,5 @@
         ]
     },
     "sw_version": "2022.2.322",
-    "generated_date": "2023-01-05T22:36:48.178317"
+    "generated_date": "2023-01-05T23:44:10.084005"
 }