Use sram instead of sdram in sim, fully switch to verilator

Makefile

@@ -1,4 +1,4 @@
-ROM_TARGET=test_code/ntw_test
+ROM_TARGET=test_code/loop_test
 
 INIT_HEX=hw/super6502_fpga/init_hex.mem
 HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin

hw/super6502_fpga/src/rtl/super_6502_fpga.sv

@@ -530,4 +530,4 @@ network_processor #(
     .s_axil_rresp   (ntw_RRESP)
 );
 
-endmodule
+endmodule

hw/super6502_fpga/src/sim/Makefile

@@ -1,7 +1,10 @@
 FPGA_SRCS_LIST=../../sources.list
 SIM_SRCS_LIST=sources.list
+BAD_SOURCES_LIST=stubs.list
 
 SUPER6502_FPGA_SOURCES=$(shell rtl-manifest $(FPGA_SRCS_LIST))
+BAD_SOURCES=$(shell rtl-manifest $(BAD_SOURCES_LIST))
+GOOD_FPGA_SOURCES=$(filter-out $(BAD_SOURCES), $(SUPER6502_FPGA_SOURCES))
 SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
 
 INCLUDE=include/sdram_controller_define.vh
@@ -24,7 +27,7 @@ waves: $(TB_NAME)
 
 $(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
 # $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
-	verilator --binary $(FLAGS) $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) +incdir+../../ -Wno-BLKANDNBLK -Wno-fatal -j 16 --top sim_top --trace-fst -Wno-ASSIGNDLY
+	verilator --binary $(FLAGS) $(INCLUDE) $(GOOD_FPGA_SOURCES) $(SIM_SOURCES) +incdir+../../ -Wno-BLKANDNBLK -Wno-fatal -j 16 --top sim_top --trace-fst -Wno-ASSIGNDLY
 
 
 $(SD_IMAGE):

hw/super6502_fpga/src/sim/hvl/sdram_sram.sv

@@ -0,0 +1,105 @@
+module sdram_controller (
+    input i_aresetn,
+    input i_sysclk,
+    input i_sdrclk,
+    input i_tACclk,
+
+    output o_pll_reset,
+    input i_pll_locked,
+
+    output o_sdr_state,
+
+    input i_AXI4_AWVALID,
+    output o_AXI4_AWREADY,
+    input [23:0] i_AXI4_AWADDR,
+    input i_AXI4_WVALID,
+    output o_AXI4_WREADY,
+    input [31:0] i_AXI4_WDATA,
+    input [3:0] i_AXI4_WSTRB,
+    output o_AXI4_BVALID,
+    input i_AXI4_BREADY,
+    input i_AXI4_ARVALID,
+    output o_AXI4_ARREADY,
+    input [23:0] i_AXI4_ARADDR,
+    output o_AXI4_RVALID,
+    input i_AXI4_RREADY,
+    output [31:0] o_AXI4_RDATA,
+
+    input i_AXI4_WLAST,
+    output o_AXI4_RLAST,
+    input [3:0] i_AXI4_AWID,
+    input [2:0] i_AXI4_AWSIZE,
+    input [3:0] i_AXI4_ARID,
+    input [7:0] i_AXI4_ARLEN,
+    input [2:0] i_AXI4_ARSIZE,
+    input [1:0] i_AXI4_ARBURST,
+    input [7:0] i_AXI4_AWLEN,
+    output [3:0] o_AXI4_RID,
+    output [3:0] o_AXI4_BID,
+
+    output [1:0] o_sdr_CKE,
+    output [1:0] o_sdr_n_CS,
+    output [1:0] o_sdr_n_RAS,
+    output [1:0] o_sdr_n_CAS,
+    output [1:0] o_sdr_n_WE,
+    output [3:0] o_sdr_BA,
+    output [25:0] o_sdr_ADDR,
+    output [31:0] o_sdr_DATA,
+    output [31:0] o_sdr_DATA_oe,
+    input [31:0] i_sdr_DATA,
+    output [3:0] o_sdr_DQM
+);
+
+assign o_sdr_state	= '1;
+
+assign o_AXI4_RLAST 	= '0;
+assign o_AXI4_RID 	= '0;
+assign o_AXI4_BID 	= '0;
+
+assign o_sdr_CKE 	= '0;
+assign o_sdr_n_CS 	= '0;
+assign o_sdr_n_RAS 	= '0;
+assign o_sdr_n_CAS 	= '0;
+assign o_sdr_n_WE 	= '0;
+assign o_sdr_BA 	= '0;
+assign o_sdr_ADDR 	= '0;
+assign o_sdr_DATA 	= '0;
+assign o_sdr_DATA_oe 	= '0;
+assign o_sdr_DQM 	= '0;
+
+
+axi4_lite_ram #(
+    .RAM_SIZE(25),
+    .ZERO_INIT(1)
+) u_sdram_emu (
+    .i_clk(i_sysclk),
+    .i_rst(~i_aresetn),
+
+    .o_AWREADY(o_AXI4_AWREADY),
+    .o_WREADY(o_AXI4_WREADY),
+
+    .o_BVALID(o_AXI4_BVALID),
+    .i_BREADY(i_AXI4_BREADY),
+    .o_BRESP(o_BRESP),
+
+    .i_ARVALID(i_AXI4_ARVALID),
+    .o_ARREADY(o_AXI4_ARREADY),
+    .i_ARADDR(i_AXI4_ARADDR),
+    .i_ARPROT('0),
+    
+    .o_RVALID(o_AXI4_RVALID),
+    .i_RREADY(i_AXI4_RREADY),
+    .o_RDATA(o_AXI4_RDATA),
+    .o_RRESP(o_AXI4_RRESP),
+
+    .i_AWVALID(i_AXI4_AWVALID),
+    .i_AWADDR(i_AXI4_AWADDR),
+    .i_AWPROT('0),
+
+    .i_WVALID(i_AXI4_WVALID),
+    .i_WDATA(i_AXI4_WDATA),
+    .i_WSTRB(i_AXI4_WSTRB)
+);
+
+
+endmodule

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -87,6 +87,7 @@ logic   [DQ_GROUP				-1:0]   w_sdr_DQM;
 wire    [DQ_GROUP	*DQ_WIDTH	-1:0]   w_sdr_DQ;
 // ^ Has to be wire because of tristate/inout stuff
 
+/*
 genvar i, j;
 generate
     for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
@@ -111,7 +112,7 @@ generate
         );
     end
 endgenerate
-
+*/
 
 // potential sd card sim here?
 
@@ -200,4 +201,4 @@ initial begin
     $finish();
 end
 
-endmodule
+endmodule

hw/super6502_fpga/src/sim/sources.list

@@ -1,9 +1,9 @@
 hvl/sim_top.sv
 sub/verilog-6502/ALU.v
 sub/verilog-6502/cpu_65c02.v
-sub/sim_sdram/generic_sdr_stub.v
+hvl/sdram_sram.sv
 ../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdio.v
 ../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdcmd.v
 ../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdrx.v
 ../sub/sd_controller_wrapper/sdspi/bench/verilog/mdl_sdtx.v
-../sub/sd_controller_wrapper/sdspi/bench/verilog/IOBUF.v
+../sub/sd_controller_wrapper/sdspi/bench/verilog/IOBUF.v

init_env.sh

@@ -15,7 +15,7 @@ python3.11 -m venv .user_venv
 pip install -r requirements.txt
 
 module load efinity/2023.1
-module load iverilog/12.0
+module load verilator
 module load gtkwave/3.3_gtk3
 
 # pip install -r requirements.txt