Start spi controller and tb

hw/efinix_fpga/simulation/Makefile

@@ -1,4 +1,4 @@
-TARGETS= timer interrupt_controller
+TARGETS= timer interrupt_controller spi_controller
 TB=$(patsubst %, %_tb.sv, $(TARGETS))
 
 all: $(TARGETS)
@@ -6,6 +6,9 @@ all: $(TARGETS)
 timer: timer_tb.sv
 	iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
 
+spi_controller: spi_controller_tb.sv
+	iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
+
 interrupt_controller: interrupt_controller_tb.sv
 	iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv