From 8721c816fcdbb09d71434ac90767b220de407541 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 23 Nov 2023 12:06:19 -0800 Subject: [PATCH] Move fast signals to fast reset --- hw/efinix_fpga/src/spi_controller.sv | 15 +++++++++++---- hw/efinix_fpga/super6502.xml | 2 +- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/efinix_fpga/src/spi_controller.sv b/hw/efinix_fpga/src/spi_controller.sv index 7175191..316de82 100644 --- a/hw/efinix_fpga/src/spi_controller.sv +++ b/hw/efinix_fpga/src/spi_controller.sv @@ -43,12 +43,8 @@ logic working; always @(negedge i_clk_cpu) begin if (i_rst) begin r_baud_rate <= 8'h1; - r_input_data <= '0; r_output_data <= '0; r_control <= '0; - r_clock_counter <= '0; - count <= '0; - spi_clk <= '0; active <= '0; end else begin active <= '0; @@ -71,8 +67,19 @@ end logic active_f; logic [7:0] r_output_data_f; +logic reset_f; +always @(posedge i_clk_50) begin + reset_f <= i_rst; +end always @(posedge i_clk_50) begin + if (reset_f) begin + r_input_data <= '0; + r_clock_counter <= '0; + count <= '0; + spi_clk <= '0; + end + if (active_f) begin r_spi_mosi <= r_output_data_f[7]; r_clock_counter <= r_clock_counter + 9'b1; diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index abac6c2..da80207 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - +