Move fast signals to fast reset
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@@ -43,12 +43,8 @@ logic working;
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always @(negedge i_clk_cpu) begin
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if (i_rst) begin
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r_baud_rate <= 8'h1;
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r_input_data <= '0;
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r_output_data <= '0;
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r_control <= '0;
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r_clock_counter <= '0;
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count <= '0;
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spi_clk <= '0;
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active <= '0;
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end else begin
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active <= '0;
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@@ -71,8 +67,19 @@ end
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logic active_f;
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logic [7:0] r_output_data_f;
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logic reset_f;
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always @(posedge i_clk_50) begin
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reset_f <= i_rst;
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end
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always @(posedge i_clk_50) begin
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if (reset_f) begin
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r_input_data <= '0;
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r_clock_counter <= '0;
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count <= '0;
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spi_clk <= '0;
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end
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if (active_f) begin
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r_spi_mosi <= r_output_data_f[7];
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r_clock_counter <= r_clock_counter + 9'b1;
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@@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Sun November 19 2023 15:04:04" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:project name="super6502" description="" last_change_date="Thu November 23 2023 12:03:00" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/>
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<efx:device name="T20F256"/>
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